Hello:
This patch was applied to netdev/net.git (master) by Jakub Kicinski kuba@kernel.org:
On Mon, 25 Apr 2022 17:20:27 +0200 you wrote:
Commit 4b5923249b8fa4 ("net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bits") added all known bits in the GSWIP_MII_CFGp register. It helped bring this register into a well-defined state so the driver has to rely less on the bootloader to do things right. Unfortunately it also sets the GSWIP_MII_CFG_RMII_CLK bit without any possibility to configure it. Upon further testing it turns out that all boards which are supported by the GSWIP driver in OpenWrt which use an RMII PHY have a dedicated oscillator on the board which provides the 50MHz RMII reference clock.
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Here is the summary with links: - [net] net: dsa: lantiq_gswip: Don't set GSWIP_MII_CFG_RMII_CLK https://git.kernel.org/netdev/net/c/71cffebf6358
You are awesome, thank you!