6.14-stable review patch. If anyone has any objections, please let me know.
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From: Nicolas Frattaroli nicolas.frattaroli@collabora.com
[ Upstream commit 73d246b4402c3356f6b3d13665de3a51eea7b555 ]
The GPIO3 A4 pin on the ArmSoM Sige5 is routed to the 40-pin GPIO header. This pin can serve a variety of functions, including ones of questionable use to us on a GPIO header such as the 25MHz clock of the ethernet controller.
Unfortunately, this is the precise function that it is being claimed for by the gmac0 node in the Sige5 board dts, meaning it can't be used for anything else despite serving no useful function in this role. Since it goes through a RS0108 bidirectional voltage level translator with a maximum data rate of 24Mbit/s in push-pull mode and 2Mbit/s data rate in open-drain mode, it's doubtful as to whether the 25MHz clock signal would even survive to the actual user-accessible pin it terminates in.
Remove it to leave the pin for users to play with. It's infinitely more useful as a GPIO or even as a PWM.
Fixes: 40f742b07ab2 ("arm64: dts: rockchip: Add rk3576-armsom-sige5 board") Signed-off-by: Nicolas Frattaroli nicolas.frattaroli@collabora.com Link: https://lore.kernel.org/r/20250314-rk3576-sige5-eth-clk-begone-v1-1-2858338f... Signed-off-by: Heiko Stuebner heiko@sntech.de Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 7c7331936a7fd..a9b9db31d2a3e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -182,8 +182,7 @@ ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>;
phy-handle = <&rgmii_phy0>; status = "okay";