Re: [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks

On Tue, 20 May 2025 11:07:42 +0200, Krzysztof Kozlowski wrote:

On SM8750 the setting rate of pixel and byte clocks, while the parent DSI PHY PLL, fails with:

disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.

DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in CMN_CTRL_0 asserted.

[...]

Applied, thanks!

[1/1] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks commit: 0acf9e65a47d1e489c8b24c45a64436e30bcccf4

Best regards,