Re: [PATCH] clk: ingenic: Fix divider calculation with div tables

Quoting Paul Cercueil (2020-12-12 05:57:33)

The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: stable@vger.kernel.org # 5.2 Signed-off-by: Paul Cercueil paul@crapouillou.net

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Applied to clk-next