Hi Lu, Jason,
On 7/17/2025 7:13 AM, Baolu Lu wrote:
On 7/16/25 20:08, Jason Gunthorpe wrote:
On Wed, Jul 16, 2025 at 02:34:04PM +0800, Baolu Lu wrote:
@@ -654,6 +656,9 @@ struct iommu_ops {
int (*def_domain_type)(struct device *dev);
+ void (*paging_cache_invalidate)(struct iommu_device *dev, + unsigned long start, unsigned long end);
How would you even implement this in a driver?
You either flush the whole iommu, in which case who needs a rage, or the driver has to iterate over the PASID list, in which case it doesn't really improve the situation.
The Intel iommu driver supports flushing all SVA PASIDs with a single request in the invalidation queue.
How? All PASID !=0 ? The HW has no notion about a SVA PASID vs no-SVA else. This is just flushing almost everything.
The intel iommu driver allocates a dedicated domain id for all sva domains. It can flush all cache entries with that domain id tagged.
AMD IOMMU has INVALIDATE_IOMMU_ALL which flushes everything in IOMMU TLB. This is heavy hammer. But should be OK for short term solution?
I don't think this command is supported inside the guest (I will double check). But we don't have HW-vIOMMU support yet. So PASID inside guest is not yet supported.
-Vasant