On Mon, 27 Jan 2025 at 18:32, Prabhakar prabhakar.csengg@gmail.com wrote:
From: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock source for HP is derived from PLL6 divided by 2. This patch corrects the implementation by configuring HP as a fixed clock source instead of a MUX.
The `CPG_PL6_ETH_SSEL` register, which is available on the RZ/G2UL SoC, is not present on the RZ/Five SoC, necessitating this change.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh hien.huynh.px@renesas.com Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v1->v2
- Fixed build warning for non-ARM64 arch, sel_pll6_2 defined but not used.
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-clk for v6.15.
Gr{oetje,eeting}s,
Geert