11 Apr
2019
11 Apr
'19
8:16 p.m.
Quoting Weiyi Lu (2019-03-04 21:05:39)
From: Owen Chen owen.chen@mediatek.com
On both MT8183 & MT6765, there add "set/clr" register for each clkmux setting, and one update register to trigger value change. It is designed to prevent read-modify-write racing issue. The sw design need to add a new API to handle this hw change with a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen owen.chen@mediatek.com Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com
Applied to clk-next