On Wed, Jun 09, 2021 at 01:50:07PM -0500, Dinh Nguyen wrote:
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that was not being accounted for. The bypass selects between emaca_clk/emacb_clk and boot_clk.
Because the bypass register offset is different between Stratix10 and Agilex/N5X, it's best to create a new function to calculate the bypass.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Signed-off-by: Dinh Nguyen dinguyen@kernel.org
drivers/clk/socfpga/clk-agilex.c | 4 +- drivers/clk/socfpga/clk-gate-s10.c | 119 +++++++++++++++++++++++++++- drivers/clk/socfpga/stratix10-clk.h | 2 + 3 files changed, 123 insertions(+), 2 deletions(-)
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This is not the correct way to submit patches for inclusion in the stable kernel tree. Please read: https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html for how to do this properly.
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