Hi Miquel,
-----Original Message----- From: Miquel Raynal miquel.raynal@bootlin.com Sent: Friday, 7 February, 2025 1:02 AM To: Rabara, Niravkumar L niravkumar.l.rabara@intel.com Cc: Richard Weinberger richard@nod.at; Vignesh Raghavendra vigneshr@ti.com; linux@treblig.org; Shen Lichuan shenlichuan@vivo.com; Jinjie Ruan ruanjinjie@huawei.com; u.kleine- koenig@baylibre.com; linux-mtd@lists.infradead.org; linux- kernel@vger.kernel.org; stable@vger.kernel.org Subject: Re: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when DMA is not ready
Hello,
My apologies for the confusion. Slave DMA terminology used in cadence nand controller bindings and driver is indeed confusing.
To answer your question it is, 1 - External DMA (Generic DMA controller).
Nand controller IP do not have embedded DMA controller (2 - peripheral
DMA).
FYR, how external DMA is used. https://elixir.bootlin.com/linux/v6.13.1/source/drivers/mtd/nand /ra w/c adence-nand-controller.c#L1962
In this case we should have a dmas property (and perhaps dma-names),
no?
No, I believe. Cadence NAND controller IP do not have dedicated handshake interface to connect with DMA controller. My understanding is dmas (and dma-names) are only used for the dedicated handshake interface between peripheral and the DMA
controller.
I don't see well how you can defer if there is no resource to grab. And if there is a resource to grab, why is it not described anywhere?
Since NAND controller do not have handshake interface with DMA
controller.
Driver is using external DMA for memory-to-memory copy.
I'm sorry you lost me again. What do you mean handshake? There is no request line? There is no way the NAND controller can trigger DMA transfers?
Yes, I mean there is no request line, so there is no way the NAND controller can trigger DMA transfer.
Sorry I used the terminology based on Synopsys DesignWare AXI DMA Controller that is used with Agilex5 SoCFPGA platform. https://github.com/torvalds/linux/blob/v6.14-rc1/drivers/dma/dw-axi-dmac/dw-...
What do you mean mem-to-mem, how is this useful to the controller?
I mean system memory to/from NAND MMIO register address for page read/write data transfer.
reg = <0x10b80000 0x10000>, <0x10840000 0x1000>; <--- This MMIO address block reg-names = "reg", "sdma";
Your point is since the driver is using external DMA and it should be described in bindings?
Yes. But maybe I still don't get it correctly.
dmas is an optional property in cadence nand controller bindings. https://github.com/torvalds/linux/blob/v6.14-rc1/Documentation/devicetree/bi... Does it need to change to required property in bindings?
Please let me know if you have any suggestion/advise.
Thanks, Nirav