On 11.2.2020 18.13, Greg KH wrote:
On Tue, Feb 11, 2020 at 04:12:40PM +0100, Marek Szyprowski wrote:
Hi Mathias,
On 11.02.2020 16:01, Mathias Nyman wrote:
xhci driver assumed that xHC controllers have at most one custom supported speed table (PSI) for all usb 3.x ports. Memory was allocated for one PSI table under the xhci hub structure.
Turns out this is not the case, some controllers have a separate "supported protocol capability" entry with a PSI table for each port. This means each usb3 roothub port can in theory support different custom speeds.
To solve this, cache all supported protocol capabilities with their PSI tables in an array, and add pointers to the xhci port structure so that every port points to its capability entry in the array.
When creating the SuperSpeedPlus USB Device Capability BOS descriptor for the xhci USB 3.1 roothub we for now will use only data from the first USB 3.1 capable protocol capability entry in the array. This could be improved later, this patch focuses resolving the memory leak.
Reported-by: Paul Menzel pmenzel@molgen.mpg.de Reported-by: Sajja Venkateswara Rao VenkateswaraRao.Sajja@amd.com Fixes: 47189098f8be ("xhci: parse xhci protocol speed ID list for usb 3.1 usage") Cc: stable stable@vger.kernel.org # v4.4+ Signed-off-by: Mathias Nyman mathias.nyman@linux.intel.com
Tested-by: Marek Szyprowski m.szyprowski@samsung.com
Nice!
Should I revert the first and then apply this?
Yes, please
Thanks
-Mathias