From: Christian Eggers
Sent: 28 July 2020 11:30
On Tuesday, 28 July 2020, 11:52:05 CEST, David Laight wrote:
From: Christian Eggers
Sent: 28 July 2020 10:30
SPI eeproms are addressed by byte.
They also support multi-byte writes - possibly with alignment restrictions. So forcing 4-byte writes (at aligned addresses) would typically speed up writes by a factor of 4 over byte writes.
So does this fix a problem? If so what.
I use the nvmem-cells property for getting the MAC-Address out of the eeprom (actually an FRAM in my case).
&spi { .... fram: fram@0 { ... mac_address_fec2: mac-address@126 { reg = <0x126 6>; }; ... }; };
Hmmmm.... the 'stride' only constrains the alignment of 'cells'. (ie address ranges from the device tree.)
It looks as though you can open the entire NVMEM device and then do reads from byte offsets. The 'stride' and 'word_size' are then not checked!
Actually it might be that before 01973a01f9ec3 byte aligned 'cells' were allowed.
David
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