On Thu, Jun 20, 2019 at 09:17:00AM +0100, Jon Hunter wrote:
The Tegra AGIC interrupt controller is an ARM GIC400 interrupt controller. Per the ARM GIC device-tree binding, the first address region is for the GIC distributor registers and the second address region is for the GIC CPU interface registers. The address space for the distributor registers is 4kB, but currently this is incorrectly defined as 8kB for the Tegra AGIC and overlaps with the CPU interface registers. Correct the address space for the distributor to be 4kB.
Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter jonathanh@nvidia.com
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to for-5.3/arm64/dt, though I also added the following Fixes: line:
Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")
Thanks, Thierry