Re: [PATCH v4 1/2] staging: iio: frequency: ad9832: Use SLEEP bit instead of RESET to disable output

On Fri, Apr 25, 2025 at 1:34 AM Gabriel Shahrouzi gshahrouzi@gmail.com wrote:

According to the AD9832 datasheet (Table 10, D12 description), setting the RESET bit forces the phase accumulator to zero, which corresponds to a full-scale DC output, rather than disabling the output signal.

The correct way to disable the output and enter a low-power state is to set the AD9832_SLEEP bit (Table 10, D13 description), which powers down the internal DAC current sources and disables internal clocks.

...

            if (val)
                    st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR);
            else

•                   st->ctrl_src |= FIELD_PREP(AD9832_RESET, 1);
  

•                   st->ctrl_src |= FIELD_PREP(AD9832_SLEEP, 1);
  

From the code perspective this allows combinations of the bits to be set. So, what does the datasheet say about SLEEP+RESET, or RESET+CLR, or other combinations of these 3 bits?