On Sun, Nov 11, 2018 at 07:36:45PM +0000, Sudip Mukherjee wrote:
Hi Greg,
This was not marked for stable but seems it should be in stable. Please apply to your queue of 4.14-stable.
-- Regards Sudip
From 0b08b65ad657c08a9b8468d64624f6df52a2f863 Mon Sep 17 00:00:00 2001
From: Chris Packham chris.packham@alliedtelesis.co.nz Date: Thu, 24 May 2018 17:23:41 +1200 Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND
commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz Signed-off-by: Stephen Boyd sboyd@kernel.org Signed-off-by: Sudip Mukherjee sudipm.mukherjee@gmail.com
drivers/clk/mvebu/clk-corediv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Now applied, thanks.
greg k-h