6.8-stable review patch. If anyone has any objections, please let me know.
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From: Sung Joon Kim sungjoon.kim@amd.com
[ Upstream commit 6f0c228ed9184287031a66b46a79e5a3d2e73a86 ]
[why] preOS will not support display mode programming and link training for UHBR rates.
[how] If we detect a sink that's UHBR capable, disable seamless boot
Reviewed-by: Anthony Koo anthony.koo@amd.com Acked-by: Wayne Lin wayne.lin@amd.com Signed-off-by: Sung Joon Kim sungjoon.kim@amd.com Tested-by: Daniel Wheeler daniel.wheeler@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3c3d613c5f00e..040b5c2a57586 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1804,6 +1804,9 @@ bool dc_validate_boot_timing(const struct dc *dc, return false; }
+ if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) + return false; + if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) { DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n"); return false;