On Mon, Aug 26, 2019 at 02:57:30PM -0500, Kim Phillips wrote:
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 62f317c9113a..f2625b4a5a8b 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -663,8 +663,15 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) out: if (throttle) perf_ibs_stop(event, 0);
- else
perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
- else {
Coding Style requires braces on both legs of a conditional.
period >>= 4;if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&(*config & IBS_OP_CNT_CTL))period |= *config & IBS_OP_CUR_CNT_RAND;perf_ibs_enable_event(perf_ibs, hwc, period);- }
perf_event_update_userpage(event); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 1392d5e6e8d6..67d94696a1d6 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -259,9 +259,12 @@ struct pebs_lbr { #define IBS_FETCH_CNT 0xFFFF0000ULL #define IBS_FETCH_MAX_CNT 0x0000FFFFULL -/* ibs op bits/masks */ -/* lower 4 bits of the current count are ignored: */ -#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32) +/* ibs op bits/masks
- The lower 7 bits of the current count are random bits
- preloaded by hardware and ignored in software
- */
Malformed comment style.
+#define IBS_OP_CUR_CNT (0xFFF80ULL<<32) +#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17)
Fixed up both issues and applied.
Thanks!