Re: [PATCH v2] net: mdio: mux-meson-gxl: set 28th bit in eth_reg2

On Mon, Mar 31, 2025 at 05:21:08PM -0400, Da Xue wrote:

I found this on the zircon kernel:

#define REG2_ETH_REG2_REVERSED (1 << 28)

pregs->Write32(REG2_ETH_REG2_REVERSED | REG2_INTERNAL_PHY_ID, PER_ETH_REG2);

I can respin and call it that.

Which interface mode is being used, and what is the MAC connected to?

"Reversed" seems to imply that _this_ end is acting as a PHY rather than the MAC in the link, so I think a bit more information (the above) is needed to ensure that this is the correct solution.