Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi"), the workaround of passing the PHY rate from DW HDMI QP bridge driver via phy_set_bus_width() became partially broken, unless the rate adjustment is done as with RK3588, i.e. by CCF from VOP2.
Attempting to fix this up at PHY level would not only introduce additional hacks, but it would also fail to adequately resolve the display issues that are a consequence of the system CRU limitations.
Therefore, let's proceed with the solution already implemented for RK3588, that is to make use of the HDMI PHY PLL as a more accurate DCLK source in VOP2.
It's worth noting a follow-up patch is going to drop the hack from the bridge driver altogether, while switching to HDMI PHY configuration API for setting up the TMDS character rate.
Signed-off-by: Cristian Ciocaltea cristian.ciocaltea@collabora.com --- Cristian Ciocaltea (3): dt-bindings: display: vop2: Add optional PLL clock property for rk3576 arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576 arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
.../bindings/display/rockchip/rockchip-vop2.yaml | 56 +++++++++++++++++----- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 7 ++- 2 files changed, 49 insertions(+), 14 deletions(-) --- base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 change-id: 20250611-rk3576-hdmitx-fix-e030fbdb0d17