On Wed, Jul 16, 2025 at 5:03 PM Alex Deucher alexdeucher@gmail.com wrote:
On Wed, Jul 16, 2025 at 12:40 PM Brian Geffon bgeffon@google.com wrote:
On Wed, Jul 16, 2025 at 12:33 PM Alex Deucher alexdeucher@gmail.com wrote:
On Wed, Jul 16, 2025 at 12:18 PM Brian Geffon bgeffon@google.com wrote:
Commit 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") allowed for newer ASICs to mix GTT and VRAM, this change also noted that some older boards, such as Stoney and Carrizo do not support this. It appears that at least one additional ASIC does not support this which is Raven.
We observed this issue when migrating a device from a 5.4 to 6.6 kernel and have confirmed that Raven also needs to be excluded from mixing GTT and VRAM.
Can you elaborate a bit on what the problem is? For carrizo and stoney this is a hardware limitation (all display buffers need to be in GTT or VRAM, but not both). Raven and newer don't have this limitation and we tested raven pretty extensively at the time.
Thanks for taking the time to look. We have automated testing and a few igt gpu tools tests failed and after debugging we found that commit 81d0bcf99009 is what introduced the failures on this hardware on 6.1+ kernels. The specific tests that fail are kms_async_flips and kms_plane_alpha_blend, excluding Raven from this sharing of GTT and VRAM buffers resolves the issue.
- Harry and Leo
This sounds like the memory placement issue we discussed last week. In that case, the issue is related to where the buffer ends up when we try to do an async flip. In that case, we can't do an async flip without a full modeset if the buffers locations are different than the last modeset because we need to update more than just the buffer base addresses. This change works around that limitation by always forcing display buffers into VRAM or GTT. Adding raven to this case may fix those tests but will make the overall experience worse because we'll end up effectively not being able to not fully utilize both gtt and vram for display which would reintroduce all of the problems fixed by 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)").
Thanks Alex, the thing is, we only observe this on Raven boards, why would Raven only be impacted by this? It would seem that all devices would have this issue, no? Also, I'm not familiar with how kms_plane_alpha_blend works, but does this also support that test failing as the cause?
Thanks again, Brian
Alex
Brian
Alex
Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") Cc: Luben Tuikov luben.tuikov@amd.com Cc: Christian König christian.koenig@amd.com Cc: Alex Deucher alexander.deucher@amd.com Cc: stable@vger.kernel.org # 6.1+ Tested-by: Thadeu Lima de Souza Cascardo cascardo@igalia.com Signed-off-by: Brian Geffon bgeffon@google.com
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 73403744331a..5d7f13e25b7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1545,7 +1545,8 @@ uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, uint32_t domain) { if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY) ||(adev->asic_type == CHIP_RAVEN))) { domain = AMDGPU_GEM_DOMAIN_VRAM; if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) domain = AMDGPU_GEM_DOMAIN_GTT;-- 2.50.0.727.gbf7dc18ff4-goog