5.15-stable review patch. If anyone has any objections, please let me know.
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From: James Clark james.clark@arm.com
[ Upstream commit d05bbad0130ff86b802e5cd6acbb6cac23b841b8 ]
The spec says this:
P0 tracing support field. The permitted values are: 0b00 Tracing of load and store instructions as P0 elements is not supported. 0b11 Tracing of load and store instructions as P0 elements is supported, so TRCCONFIGR.INSTP0 is supported.
All other values are reserved.
The value we are looking for is 0b11 so simplify this. The double read and && was a bit obfuscated.
Suggested-by: Suzuki Poulose suzuki.poulose@arm.com Signed-off-by: James Clark james.clark@arm.com Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com Stable-dep-of: 46bf8d7cd853 ("coresight: etm4x: Safe access for TRCQCLTR") Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d3c11e305e5b9..fd753669b33eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1048,7 +1048,7 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + if (BMVAL(etmidr0, 1, 2) == 0b11) drvdata->instrp0 = true; else drvdata->instrp0 = false;