On Mon, 25 Aug 2025, Peter Zijlstra wrote:
On Mon, Aug 25, 2025 at 06:03:23PM +1000, Finn Thain wrote:
On Mon, 25 Aug 2025, Peter Zijlstra wrote:
And your architecture doesn't trap on unaligned atomic access ?!!?!
Right. This port doesn't do SMP.
There is RMW_INSN which seems to imply a compare-and-swap instruction of sorts. That is happy to work on unaligned storage?
Yes, the TAS and CAS instructions are happy to work on unaligned storage.
However, these operations involve an indivisible bus cycle that hogs the bus to the detriment of other processors, DMA controllers etc. So I suspect lock alignment would tend to shorten read-modify-write cycles, and improve efficiency, when CONFIG_RMW_INSN is enabled.
Most m68k platforms will have CONFIG_RMW_INSN disabled, or else simply don't implement TAS and CAS. In this case, lock alignment might still help, just because L1 cache entries are long words. I've not tried to measure this.