The GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK bit enable the feature of internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. This feature is applicable when core is operating in 2.0 device mode.
When this bit is set in host mode and core is in 2.0 device mode (maximum speed = high-speed) then usb super speed devices not detected on host.
To address the above issue added usb device mode conditional check.
Cc: stable@vger.kernel.org Fixes: 62b20e6e0dde ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode") Signed-off-by: Piyush Mehta piyush.mehta@amd.com --- DWC3 Register Map Link: https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/GUCTL1-USB3... Register Name GUCTL1 Bit: 26 Bit Name: DEV_FORCE_20_CLK_FOR_30_CLK
Change in V2: - Added CC stable kernel email.
Link: https://lore.kernel.org/all/20231005102725.8458-1-piyush.mehta@amd.com/ --- drivers/usb/dwc3/core.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c6bf054f15d..0cf1fe60628b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1202,6 +1202,7 @@ static int dwc3_core_init(struct dwc3 *dwc) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && + (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) && (dwc->maximum_speed == USB_SPEED_HIGH || dwc->maximum_speed == USB_SPEED_FULL)) reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;