Am Dienstag, 13. September 2022, 00:48:01 CEST schrieb Conor Dooley:
From: Palmer Dabbelt palmer@rivosinc.com
This fixes two issues: I truncated the warning's hart ID when porting to the 64-bit hart ID code, and the original code's warning handling could fire on an uninitialized hart ID.
The biggest change here is that riscv_cbom_block_size is no longer initialized, as IMO the default isn't sane: there's nothing in the ISA that mandates any specific cache block size, so falling back to one will just silently produce the wrong answer on some systems. This also changes the probing order so the cache block size is known before enabling Zicbom support.
CC: stable@vger.kernel.org CC: Andrew Jones ajones@ventanamicro.com CC: Heiko Stuebner heiko@sntech.de CC: Atish Patra atishp@rivosinc.com Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant") Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension") Reported-by: kernel test robot lkp@intel.com Reported-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt palmer@rivosinc.com [Conor: fixed the redefinition errors] Tested-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: Conor Dooley conor.dooley@microchip.com
Reviewed-by: Heiko Stuebner heiko@sntech.de