Re: [PATCH v4 3/3] drm/i915/gt: Enable only one CCS for compute workload

Hi Matt,

...

+static void intel_gt_apply_ccs_mode(struct intel_gt *gt) +{

• u32 mode;
• int cslice;
• if (!IS_DG2(gt->i915))

• return;
  

• /* Set '0' as a default CCS id to all the cslices */
• mode = 0;
• for (cslice = 0; cslice < hweight32(CCS_MASK(gt)); cslice++)

• /* Write 0x7 if no CCS context dispatches to this cslice */
  

• if (!(CCS_MASK(gt) & BIT(cslice)))
  

• 	mode |= XEHP_CCS_MODE_CSLICE(cslice,
  

• 				     XEHP_CCS_MODE_CSLICE_MASK);
  

• intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);

This is still going to hook all available cslices up to hardware engine ccs0. But what you actually want is to hook them all up to what userspace sees as CCS0 (i.e., the first CCS engine that wasn't fused off). Hardware's engine numbering and userspace's numbering aren't the same.

Yes, correct... we had so many discussions and I forgot about it :-)

Also, if you have a part that only has hardware ccs1/cslice1 for example, you're not going to set cslices 2 & 3 to 0x7 properly.

Good point also here, the XEHP_CCS_MODE register is indeed generic to all platforms.

So probably what you want is something like this (untested):

static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt));

    /*
     * Re-assign every present cslice to the first available CCS
     * engine; mark unavailable cslices as unused.
     */
    for (int cslice = 0; cslice < 4; cslice++) {
            if (CCS_MASK(gt) & BIT(cslice))
                    mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
            else
                    mode |= XEHP_CCS_MODE_CSLICE(cslice,
                                                 XEHP_CCS_MODE_CSLICE_MASK);
    }

    intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);

}

...

+}

int intel_gt_init_hw(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; @@ -195,6 +215,9 @@ int intel_gt_init_hw(struct intel_gt *gt) intel_gt_init_swizzling(gt);

• /* Configure CCS mode */
• intel_gt_apply_ccs_mode(gt);

This is only setting this once during init. The value gets lost on every RCS/CCS reset, so we need to make sure it gets reapplied when necessary. That means you either need to add this to the GuC regset, or you need to implement the programming as a "fake workaround" so that the workaround framework will take care of the re-application for you.

OK, I'll hook everything up in the ccs_engine_wa_init().

Thanks, Andi