On Mon, 04 Oct 2021 15:06:53 +0100, Lorenzo Pieralisi lorenzo.pieralisi@arm.com wrote:
[+Marc - always better to have his eyes on IRQ handling code]
On Fri, Oct 01, 2021 at 09:58:49PM +0200, Marek Behún wrote:
From: Pali Rohár pali@kernel.org
It is incorrect to clear status bits of masked interrupts.
The aardvark driver clears all status interrupt bits if no unmasked status bit is set. Masked bits should never be cleared.
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár pali@kernel.org Reviewed-by: Marek Behún kabel@kernel.org Signed-off-by: Marek Behún kabel@kernel.org Cc: stable@vger.kernel.org
drivers/pci/controller/pci-aardvark.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index d5d6f92e5143..e4986806a189 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1295,11 +1295,8 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
- if (!isr0_status && !isr1_status) {
advk_writel(pcie, isr0_val, PCIE_ISR0_REG);advk_writel(pcie, isr1_val, PCIE_ISR1_REG);This looks fine - on the other hand if no interrupt is set in the status registers (that are filtered with the masks) we are dealing with a spurious IRQ right ? Just gauging how severe this is.
Lorenzo
- if (!isr0_status && !isr1_status) return;
The whole thing is a bit odd. What the commit message doesn't say is whether the status register shows the status of the line before masking, or after masking.
The code seems to imply the former, but then the behaviour is awkward. How did we end-up here the first place? if that's only a spurious interrupt, then I'd probably simplify the code altogether, and drop all the early return code. Something like below, as usual completely untested.
M.
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 596ebcfcc82d..1d8f257ecb63 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1275,7 +1275,8 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) static void advk_pcie_handle_int(struct advk_pcie *pcie) { u32 isr0_val, isr0_mask, isr0_status; - u32 isr1_val, isr1_mask, isr1_status; + u32 isr1_val, isr1_mask; + unsigned long isr1_status; int i;
isr0_val = advk_readl(pcie, PCIE_ISR0_REG); @@ -1285,22 +1286,14 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) isr1_val = advk_readl(pcie, PCIE_ISR1_REG); isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); - - if (!isr0_status && !isr1_status) { - advk_writel(pcie, isr0_val, PCIE_ISR0_REG); - advk_writel(pcie, isr1_val, PCIE_ISR1_REG); - return; - } + isr1_status >> 8;
/* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) advk_pcie_handle_msi(pcie);
/* Process legacy interrupts */ - for (i = 0; i < PCI_NUM_INTX; i++) { - if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) - continue; - + for_each_set_bit(i, &isr1_status, PCI_NUM_INTX) { advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), PCIE_ISR1_REG);