commit b8c5d882c833 upstream
This patch should have made it into kernel version 5.4 as it fixes some major stability issue running on Marvell A7K/A8K, for which it was originally developed, which was introduced by an earlier patch. It is identical to the upstream patch, save for some whitespace fixes that were removed to not violate the "no trivial fixes" rule. Below follows the original patch text as submitted for kernel 5.5.
This patch corrects an error in the Transform Record Cache initialization code that was causing intermittent stability problems on the Macchiatobin board.
Unfortunately, due to HW platform specifics, the problem could not happen on the main development platform, being the VCU118 Xilinx development board. And since it was a problem with hash table access, it was very dependent on the actual physical context record DMA buffers being used, i.e. with some (bad) luck it could seemingly work quit stable for a while.
Fixes: 465527bcaebc ("crypto: inside-secure - Probe transform record cache RAM sizes") Signed-off-by: Pascal van Leeuwen pvanleeuwen@verimatrix.com --- drivers/crypto/inside-secure/safexcel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/inside-secure/safexcel.c b/drivers/crypto/inside-secure/safexcel.c index 4ab1bde..40adf8c 100644 --- a/drivers/crypto/inside-secure/safexcel.c +++ b/drivers/crypto/inside-secure/safexcel.c @@ -223,7 +223,7 @@ static void eip197_trc_cache_init(struct safexcel_crypto_priv *priv) /* Step #4: determine current size of hash table in dwords */ cs_ht_wc = 16<<cs_ht_sz; /* dwords, not admin words */ /* Step #5: add back excess words and see if we can fit more records */ - cs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 4)); + cs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 2));
/* Clear the cache RAMs */ eip197_trc_cache_clear(priv, cs_rc_max, cs_ht_wc);