Re: [PATCH 1/2] mtd: spi-nor: spansion: Consider reserved bits in CFR5 register

On 10.01.2023 18:47, Tudor Ambarus wrote:

CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS} definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future possible addition of Octal STR mode support.

Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Cc:stable@vger.kernel.org Reported-by: Takahiro KuwanoTakahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarustudor.ambarus@linaro.org

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drivers/mtd/spi-nor/spansion.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)

both applied, thanks!