On Thu, 31 Jul 2025 at 21:29, Dave Hansen dave.hansen@intel.com wrote:
On 7/29/25 21:26, Suchit Karunakaran wrote:
The logic to synthesize constant_tsc for Pentium 4s (Family 15) is wrong. Since INTEL_P4_PRESCOTT is numerically greater than INTEL_P4_WILLAMETTE, the logic always results in false and never sets X86_FEATURE_CONSTANT_TSC for any Pentium 4 model. The error was introduced while replacing the x86_model check with a VFM one. The original check was as follows: if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
Fix the logic to cover all Pentium 4 models from Prescott (model 3) to Cedarmill (model 6) which is the last model released in Family 15.
Could we have a slightly different changelog, please? The fact that the logic results in the bit never getting set for P4's is IMNHO immaterial. This looks like a plain and simple typo, not a logical error on the patch author's part.
How about this as a changelog?
--
Pentium 4's which are INTEL_P4_PRESCOTT (mode 0x03) and later have a constant TSC. This was correctly captured until fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, the model was transposed from 0x03 to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model.
Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which is the last P4 model.
Yeah, I agree it's more of a typo than a logical error.