Wiadomość napisana przez Cristian Ciocaltea cristian.ciocaltea@collabora.com w dniu 11 cze 2025, o godz. 23:47:
Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi"), the workaround of passing the rate from DW HDMI QP bridge driver via phy_set_bus_width() became partially broken, as it cannot reliably handle mode switches anymore.
Attempting to fix this up at PHY level would not only introduce additional hacks, but it would also fail to adequately resolve the display issues that are a consequence of the system CRU limitations.
Instead, proceed with the solution already implemented for RK3588: make use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This will not only address the aforementioned problem, but it should also facilitate the proper operation of display modes up to 4K@60Hz.
It's worth noting that anything above 4K@30Hz still requires high TMDS clock ratio and scrambling support, which hasn't been mainlined yet.
Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea cristian.ciocaltea@collabora.com
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 6a13fe0c3513fb2ff7cd535aa70e3386c37696e4..b1ac23035dd789f0478bf10c78c74ef167d94904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1155,12 +1155,14 @@ vop: vop@27d00000 { <&cru HCLK_VOP>, <&cru DCLK_VP0>, <&cru DCLK_VP1>,
- <&cru DCLK_VP2>;
- <&cru DCLK_VP2>,
- <&hdptxphy>;
clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1",
"dclk_vp2";
"dclk_vp2","pll_hdmiphy0";iommus = <&vop_mmu>; power-domains = <&power RK3576_PD_VOP>; rockchip,grf = <&sys_grf>;
-- 2.49.0
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Cristian, It fixes fractional hd modes for me on rk3576. Thx for this fix!