Hi Wayne,
On 07/05/2025 03:48, Wayne Chang wrote:
The logic that drives the pad calibration values resides in the controller reset domain and so the calibration values are only being captured when the controller is out of reset. However, by clearing the CYA_TRK_CODE_UPDATE_ON_IDLE bit, the calibration values can be set while the controller is in reset.
The CYA_TRK_CODE_UPDATE_ON_IDLE bit was previously cleared based on the trk_hw_mode flag, but this dependency is not necessary. Instead, introduce a new flag, trk_update_on_idle, to independently control this bit.
Fixes: d8163a32ca95 ("phy: tegra: xusb: Add Tegra234 support") Cc: stable@vger.kernel.org Signed-off-by: Wayne Chang waynec@nvidia.com
drivers/phy/tegra/xusb-tegra186.c | 14 ++++++++------ drivers/phy/tegra/xusb.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index fae6242aa730..dd0aaf305e90 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -650,14 +650,15 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) udelay(100); }
- if (padctl->soc->trk_hw_mode) {
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);value |= USB2_TRK_HW_MODE;
- value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
- if (padctl->soc->trk_update_on_idle) value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);- } else {
- if (padctl->soc->trk_hw_mode)
value |= USB2_TRK_HW_MODE;- padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
- if (!padctl->soc->trk_hw_mode) clk_disable_unprepare(priv->usb2_trk_clk);
- }
mutex_unlock(&padctl->lock);
Can we rebase this on top of the fix 'phy: tegra: xusb: remove a stray unlock'? This does not apply on top of that patch.
Thanks Jon