From: Devi Priya quic_devipriy@quicinc.com
[ Upstream commit 6fb45762691d12d9812c41d20b2f5db1412047ae ]
Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR registers lie in the second 4kB region. Also, add target CPU encoding.
Fixes: 97cb36ff52a1 ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support") Signed-off-by: Devi Priya quic_devipriy@quicinc.com Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230425084010.15581-2-quic_devipriy@quicinc.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 0ed19fbf7d87d..6e3a88ee06152 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -173,14 +173,14 @@ blsp1_uart2: serial@78b1000 { intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ - <0x0b002000 0x1000>, /* GICC */ + <0x0b002000 0x2000>, /* GICC */ <0x0b001000 0x1000>, /* GICH */ - <0x0b004000 0x1000>; /* GICV */ + <0x0b004000 0x2000>; /* GICV */ #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ranges = <0 0x0b00c000 0x3000>;
v2m0: v2m@0 {