On 4/10/25 22:20, Rob Herring wrote:
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Are you suggesting that this patch is not required for 6.12.y backport ? We need this commit for ID_AA64DFR0_EL1_PMUVer_V3P9 definition. Should this change be added in the last commit itself in the series instead ?
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..74fb5af91d4f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1238,6 +1238,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer @@ -2178,6 +2179,13 @@ Field 4 P Field 3:0 ALIGN EndSysreg