From: Kan Liang kan.liang@linux.intel.com
The only difference between 5 and 6 is the new counters snapshotting group, without the following counters snapshotting enabling patches, it's impossible to utilize the feature in a PEBS record. It's safe to share the same code path with format 5.
Add format 6, so the end user can at least utilize the legacy PEBS features.
Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support") Signed-off-by: Kan Liang kan.liang@linux.intel.com Cc: stable@vger.kernel.org ---
New patch since V4
arch/x86/events/intel/ds.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 8dcf90f6fb59..ba74e1198328 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2551,6 +2551,7 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; break;
+ case 6: case 5: x86_pmu.pebs_ept = 1; fallthrough;