From: Conor Dooley conor.dooley@microchip.com
[ Upstream commit efa310ba00716d7a872bdc5fa1f5545edc9efd69 ]
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla sudeep.holla@arm.com Reviewed-by: Daire McNamara daire.mcnamara@microchip.com Signed-off-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index f44fce1fe080..2f75e39d2fdd 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -51,6 +51,7 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay";
cpu1_intc: interrupt-controller { @@ -78,6 +79,7 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay";
cpu2_intc: interrupt-controller { @@ -105,6 +107,7 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay";
cpu3_intc: interrupt-controller { @@ -132,6 +135,7 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>;