On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote:
On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
Quoting Kenneth Graunke (2018-01-04 19:38:05)
Geminilake requires the 3D driver to select whether barriers are intended for compute shaders, or tessellation control shaders, by whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when switching pipelines. Failure to do this properly can result in GPU hangs.
Unfortunately, this means it needs to switch mid-batch, so only userspace can properly set it. To facilitate this, the kernel needs to whitelist the register.
Signed-off-by: Kenneth Graunke kenneth@whitecape.org Cc: stable@vger.kernel.org
drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ 2 files changed, 7 insertions(+)
Hello,
We unfortunately need to whitelist an extra register for GPU hang fix on Geminilake. Here's the corresponding Mesa patch:
Thankfully it appears to be context saved. Has a w/a name been assigned for this? -Chris
There doesn't appear to be one. The workaround page lists it, but there is no name. The register description has a note saying that you need to set this, but doesn't call it out as a workaround.
It mentions only BXT:ALL, but not mention to GLK.
Should we add to both then?
That's why I put a generic comment, rather than the name.
On Display side we started using the row name for this case, to help easily finding this later.
ex: "Display WA #0390: skl,kbl"
The number for this apparently is: WA #0862
Maybe we could use this one to start /* GT WA #0862: bxt,glk */
GT? GEM? Unnamed WA #0862?
Thanks, Rodrigo.
--Ken
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