On 9/11/2024 1:14 AM, Jason Gunthorpe wrote:

From: Eliav Bar-ilan eliavb@nvidia.com

An incorrect argument order calling amd_iommu_dev_flush_pasid_pages() causes improper flushing of the IOMMU, leaving the old value of GCR3 from a previous process attached to the same PASID.

The function has the signature:

void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, ioasid_t pasid, u64 address, size_t size)

Correct the argument order.

Cc: stable@vger.kernel.org Fixes: 474bf01ed9f0 ("iommu/amd: Add support for device based TLB invalidation") Signed-off-by: Eliav Bar-ilan eliavb@nvidia.com Signed-off-by: Jason Gunthorpe jgg@nvidia.com

Thanks for fixing. I missed to pass param's in right order after rearranging function params.

Reviewed-by: Vasant Hegde vasant.hegde@amd.com

-Vasant

---

drivers/iommu/amd/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

This was discovered while testing SVA, but I suppose it is probably a bigger issue.

diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b19e8c0f48fa25..6bc4030a6ba8ed 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1552,8 +1552,8 @@ void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data, ioasid_t pasid) {

• amd_iommu_dev_flush_pasid_pages(dev_data, 0,

• 			CMD_INV_IOMMU_ALL_PAGES_ADDRESS, pasid);
  

• amd_iommu_dev_flush_pasid_pages(dev_data, pasid, 0,

• 			CMD_INV_IOMMU_ALL_PAGES_ADDRESS);
  

} void amd_iommu_domain_flush_complete(struct protection_domain *domain)

base-commit: cf2840f59119f41de3d9641a8b18a5da1b2cf6bf