On Thu, May 18, 2023 at 05:43:51AM +0000, Vasant Hegde wrote:

IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual address space. Current code assumes it can support 64bit IOVA address space. If IOVA allocator allocates virtual address > 47/56 bit (depending on page table level) then it will do wrong mapping and cause invalid translation.

Hence adjust aperture size to use max address supported by the page table.

Reported-by: Jerry Snitselaar jsnitsel@redhat.com Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") Cc: Stable@vger.kernel.org # v6.0+ Cc: Suravee Suthikulpanit suravee.suthikulpanit@amd.com Signed-off-by: Vasant Hegde vasant.hegde@amd.com

---

drivers/iommu/amd/iommu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5aaa4cf84506..e14c7c666745 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2128,6 +2128,15 @@ static struct protection_domain *protection_domain_alloc(unsigned int type) return NULL; } +static inline u64 dma_max_address(void) +{

• if (amd_iommu_pgtable == AMD_IOMMU_V1)

• return ~0ULL;
  

• /* V2 with 4/5 level page table */
• return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1);

Hi Vasant,

For the stable releases, this will need to be PAGE_MODE_4_LEVEL instead of amd_iommu_gpt_level? The 6.4 merge window is when amd_iommu_gpt_level arrived with the 5 level page table changes.

Regards, Jerry

+}

static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) { struct protection_domain *domain; @@ -2144,7 +2153,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) return NULL; domain->domain.geometry.aperture_start = 0;

• domain->domain.geometry.aperture_end = ~0ULL;

• domain->domain.geometry.aperture_end = dma_max_address(); domain->domain.geometry.force_aperture = true;

return &domain->domain; -- 2.31.1