Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com --- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
In htvec_reset() only the first group of initial interrupts is cleared. This sometimes causes spurious interrupts, so let's clear all groups.
BTW, commit c47e388cfc648421bd821f ("irqchip/loongson-htvec: Support 8 groups of HT vectors") increase interrupt lines from 4 to 8, so update comments as well.
Cc: stable@vger.kernel.org Fixes: 818e915fbac518e8c78e1877 ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by: Huacai Chen chenhc@lemote.com --- drivers/irqchip/irq-loongson-htvec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c index 13e6016..6392aaf 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -151,7 +151,7 @@ static void htvec_reset(struct htvec *priv) /* Clear IRQ cause registers, mask all interrupts */ for (idx = 0; idx < priv->num_parents; idx++) { writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx); - writel_relaxed(0xFFFFFFFF, priv->base); + writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx); } }
@@ -172,7 +172,7 @@ static int htvec_of_init(struct device_node *node, goto free_priv; }
- /* Interrupt may come from any of the 4 interrupt line */ + /* Interrupt may come from any of the 8 interrupt lines */ for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { parent_irq[i] = irq_of_parse_and_map(node, i); if (parent_irq[i] <= 0)
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com --- drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@
struct pch_pic { void __iomem *base; + struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock; @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) { + int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain; - int err;
priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; }
+ base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); + if (base < 0) { + pr_err("Failed to allocate LPC IRQ numbers\n"); + goto iounmap_base; + } + + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, + &irq_domain_simple_ops, NULL); + if (!priv->lpc_domain) { + pr_err("Failed to add irqdomain for LPC controller"); + goto iounmap_base; + } + + for (i = 0; i < NR_IRQS_LEGACY; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); + priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),
在 2020/9/9 12:09, Huacai Chen 写道:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
It doesn't make sense at all.
How can you allocate IRQ without irqchip backing it?
- Jiaxun
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@ struct pch_pic { void __iomem *base;
- struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock;
@@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) {
- int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain;
- int err;
priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; }
- base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0);
- if (base < 0) {
pr_err("Failed to allocate LPC IRQ numbers\n");goto iounmap_base;- }
- priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0,
&irq_domain_simple_ops, NULL);- if (!priv->lpc_domain) {
pr_err("Failed to add irqdomain for LPC controller");goto iounmap_base;- }
- for (i = 0; i < NR_IRQS_LEGACY; i++)
irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq);- priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),
Hi, Jiaxun,
On Thu, Sep 10, 2020 at 8:52 AM Jiaxun Yang jiaxun.yang@flygoat.com wrote:
在 2020/9/9 12:09, Huacai Chen 写道:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
It doesn't make sense at all.
How can you allocate IRQ without irqchip backing it?
- Jiaxun
As you know, this patch resolves the kdump problem, and 0~15 is really needed to reserve for LPC, right?
Huacai
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@
struct pch_pic { void __iomem *base;
struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock;@@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) {
int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain;
int err; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv)@@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; }
base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0);if (base < 0) {pr_err("Failed to allocate LPC IRQ numbers\n");goto iounmap_base;}priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0,&irq_domain_simple_ops, NULL);if (!priv->lpc_domain) {pr_err("Failed to add irqdomain for LPC controller");goto iounmap_base;}for (i = 0; i < NR_IRQS_LEGACY; i++)irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq);priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),
On 2020-09-09 05:09, Huacai Chen wrote:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
How can they be spurious? Why are they enabled the first place?
This looks like you are papering over a much bigger issue.
M.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@
struct pch_pic { void __iomem *base;
- struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock;
@@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) {
- int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain;
int err;
priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv)
@@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; }
- base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0);
- if (base < 0) {
pr_err("Failed to allocate LPC IRQ numbers\n");goto iounmap_base;- }
- priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0,
&irq_domain_simple_ops, NULL);- if (!priv->lpc_domain) {
pr_err("Failed to add irqdomain for LPC controller");goto iounmap_base;- }
- for (i = 0; i < NR_IRQS_LEGACY; i++)
irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq);- priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),
Hi, Marc,
On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
How can they be spurious? Why are they enabled the first place?
This looks like you are papering over a much bigger issue.
The spurious interrupts are probably occurred after kdump and the irq number is in legacy LPC ranges. I think this is because the old kernel doesn't (and it can't) disable devices properly so there are stale interrupts in the kdump case.
Huacai
M.Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@
struct pch_pic { void __iomem *base;
struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock;@@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) {
int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain;
int err; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv)@@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; }
base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0);if (base < 0) {pr_err("Failed to allocate LPC IRQ numbers\n");goto iounmap_base;}priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0,&irq_domain_simple_ops, NULL);if (!priv->lpc_domain) {pr_err("Failed to add irqdomain for LPC controller");goto iounmap_base;}for (i = 0; i < NR_IRQS_LEGACY; i++)irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq);priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),-- Jazz is not dead. It just smells funny...
On 2020-09-11 05:13, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
How can they be spurious? Why are they enabled the first place?
This looks like you are papering over a much bigger issue.
The spurious interrupts are probably occurred after kdump and the irq number is in legacy LPC ranges. I think this is because the old kernel doesn't (and it can't) disable devices properly so there are stale interrupts in the kdump case.
I don't really understand why the old kernel can't turn the interrupts off. Most architectures are able t, why not yours?
Finally, why don't you just shut these interrupts off the first place in the interrupt controller init? Adding a whole lot of kernel data structures as a band-aid doesn't strike me as the best possible idea. Not to mention that if they keep firing, all you are doing is adding extra overhead.
M.
Hi, Marc,
On Fri, Sep 11, 2020 at 3:50 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 05:13, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts.
How can they be spurious? Why are they enabled the first place?
This looks like you are papering over a much bigger issue.
The spurious interrupts are probably occurred after kdump and the irq number is in legacy LPC ranges. I think this is because the old kernel doesn't (and it can't) disable devices properly so there are stale interrupts in the kdump case.
I don't really understand why the old kernel can't turn the interrupts off. Most architectures are able t, why not yours?
Finally, why don't you just shut these interrupts off the first place in the interrupt controller init? Adding a whole lot of kernel data structures as a band-aid doesn't strike me as the best possible idea. Not to mention that if they keep firing, all you are doing is adding extra overhead.
After tests, I found that the previous patch (patch 2 in this series) can avoid most spurious interrupts and kdump can work, so I will send V2 to drop this patch.
Huacai
M.-- Jazz is not dead. It just smells funny...
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Build OK! v5.4.63: Failed to apply! Possible dependencies: 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
v4.19.143: Failed to apply! Possible dependencies: 0145beed9d26 ("irqchip: davinci-aintc: move the driver to drivers/irqchip") 06a287161429 ("ARM: davinci: aintc: use the new config structure") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 2b6a2e74f2bf ("ARM: davinci: aintc: use a common prefix for symbols in the driver") 2d242aa28892 ("ARM: davinci: aintc: drop GPL license boilerplate") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 74b0eac24259 ("ARM: davinci: aintc: use irq domain") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") a98ca73ee348 ("ARM: davinci: wrap HW interrupt numbers with a macro") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") d0064594f20a ("ARM: davinci: select GENERIC_IRQ_MULTI_HANDLER") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") de4f82a245ce ("ARM: davinci: aintc: wrap davinci_irq_init() with a helper") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") fd0f4275864d ("ARM: davinci: aintc: use the new irqchip config structure in dm* SoCs")
v4.14.196: Failed to apply! Possible dependencies: 0149385537e6 ("irqchip: Place CONFIG_SIFIVE_PLIC into the menu") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") 33c57c0d3c67 ("RISC-V: Add a basic defconfig") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") 4a632cec8884 ("RISC-V: Enable module support in defconfig") 67d2075ad695 ("dt-bindings: irqchip: Introduce TISCI Interrupt router bindings") 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") abe45fd9f1b0 ("irqchip: Andestech Internal Vector Interrupt Controller driver") accaf1fbfb5d ("dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") c94fb639d546 ("irqchip: Add Kconfig menu") ca1c4d653524 ("MAINTAINERS: Add entry for sound/soc/ti and update the OMAP audio support") cd844b0715ce ("irqchip/ti-sci-intr: Add support for Interrupt Router driver") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.9.235: Failed to apply! Possible dependencies: 0464a53eba0a ("MIPS: Update Goldfish RTC driver maintainer email address") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") 33c57c0d3c67 ("RISC-V: Add a basic defconfig") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") 4a632cec8884 ("RISC-V: Enable module support in defconfig") 5ed34d3a4387 ("irqchip: Add UniPhier AIDET irqchip driver") 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") 7a08de1d8fd2 ("dt-bindings: Add device tree binding for Goldfish RTC driver") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") c94fb639d546 ("irqchip: Add Kconfig menu") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver") f22d9cdcb5eb ("rtc: goldfish: Add RTC driver for Android emulator") f48e699ddf70 ("irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed") f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.4.235: Failed to apply! Possible dependencies: 19afc3d269fe ("irqchip: i8259: Allow platforms to override poll function") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 3900d6a85e66 ("ARM: EXYNOS: Split up exynos5250 SoC specific PMU data") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 73d72ed8e98c ("ARM: EXYNOS: Split up exynos4 SoC specific PMU data") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8438aef01d35 ("ARM: EXYNOS: Remove redundant code from regs-pmu.h") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") bfce552d0b10 ("drivers: soc: Add support for Exynos PMU driver") c21100c94dfa ("ARM: EXYNOS: Split up exynos3250 SoC specific PMU data") d3bafff78331 ("ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") e32465429490 ("ARM: use "depends on" for SoC configs instead of "if" after prompt") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
Hi, Sasha,
On Fri, Sep 11, 2020 at 1:18 AM Sasha Levin sashal@kernel.org wrote:
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Build OK! v5.4.63: Failed to apply! Possible dependencies: 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
v4.19.143: Failed to apply! Possible dependencies: 0145beed9d26 ("irqchip: davinci-aintc: move the driver to drivers/irqchip") 06a287161429 ("ARM: davinci: aintc: use the new config structure") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 2b6a2e74f2bf ("ARM: davinci: aintc: use a common prefix for symbols in the driver") 2d242aa28892 ("ARM: davinci: aintc: drop GPL license boilerplate") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 74b0eac24259 ("ARM: davinci: aintc: use irq domain") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") a98ca73ee348 ("ARM: davinci: wrap HW interrupt numbers with a macro") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") d0064594f20a ("ARM: davinci: select GENERIC_IRQ_MULTI_HANDLER") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") de4f82a245ce ("ARM: davinci: aintc: wrap davinci_irq_init() with a helper") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") fd0f4275864d ("ARM: davinci: aintc: use the new irqchip config structure in dm* SoCs")
v4.14.196: Failed to apply! Possible dependencies: 0149385537e6 ("irqchip: Place CONFIG_SIFIVE_PLIC into the menu") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") 33c57c0d3c67 ("RISC-V: Add a basic defconfig") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") 4a632cec8884 ("RISC-V: Enable module support in defconfig") 67d2075ad695 ("dt-bindings: irqchip: Introduce TISCI Interrupt router bindings") 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") abe45fd9f1b0 ("irqchip: Andestech Internal Vector Interrupt Controller driver") accaf1fbfb5d ("dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") c94fb639d546 ("irqchip: Add Kconfig menu") ca1c4d653524 ("MAINTAINERS: Add entry for sound/soc/ti and update the OMAP audio support") cd844b0715ce ("irqchip/ti-sci-intr: Add support for Interrupt Router driver") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.9.235: Failed to apply! Possible dependencies: 0464a53eba0a ("MIPS: Update Goldfish RTC driver maintainer email address") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") 33c57c0d3c67 ("RISC-V: Add a basic defconfig") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") 4a632cec8884 ("RISC-V: Enable module support in defconfig") 5ed34d3a4387 ("irqchip: Add UniPhier AIDET irqchip driver") 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") 7a08de1d8fd2 ("dt-bindings: Add device tree binding for Goldfish RTC driver") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") c94fb639d546 ("irqchip: Add Kconfig menu") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver") f22d9cdcb5eb ("rtc: goldfish: Add RTC driver for Android emulator") f48e699ddf70 ("irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed") f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.4.235: Failed to apply! Possible dependencies: 19afc3d269fe ("irqchip: i8259: Allow platforms to override poll function") 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") 3900d6a85e66 ("ARM: EXYNOS: Split up exynos5250 SoC specific PMU data") 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") 73d72ed8e98c ("ARM: EXYNOS: Split up exynos4 SoC specific PMU data") 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") 8438aef01d35 ("ARM: EXYNOS: Remove redundant code from regs-pmu.h") a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") bfce552d0b10 ("drivers: soc: Add support for Exynos PMU driver") c21100c94dfa ("ARM: EXYNOS: Split up exynos3250 SoC specific PMU data") d3bafff78331 ("ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly") dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") e32465429490 ("ARM: use "depends on" for SoC configs instead of "if" after prompt") ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
This patch is only needed in 5.8+
Huacai
-- Thanks Sasha
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
M.
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
Huacai
M.-- Jazz is not dead. It just smells funny...
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
M.
Hi, Marc,
On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256)
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ.
Huacai
M.-- Jazz is not dead. It just smells funny...
On 2020-09-11 09:43, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256)
What does MIDDLE_IRQS mean? Please name it to something that actually relates to its usage...
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ.
It'd be worth considering putting some efforts there...
M.
Hi, Marc,
On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 09:43, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256)
What does MIDDLE_IRQS mean? Please name it to something that actually relates to its usage...
INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by middle nodes (not leaf nodes and not root node), midde nodes is not directed by devices, but they consumes irq numbers.
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ.
It'd be worth considering putting some efforts there...
Yes, but that is another topic.
Huacai
M.-- Jazz is not dead. It just smells funny...
On 2020-09-11 10:14, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 09:43, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote: > Modernized Loongson64 uses a hierarchical organization for interrupt > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > is not enough to represent all interrupts, so let's increase NR_IRQS to > 320. > > Cc: stable@vger.kernel.org > Signed-off-by: Huacai Chen chenhc@lemote.com > --- > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > b/arch/mips/include/asm/mach-loongson64/irq.h > index f5e362f7..0da3017 100644 > --- a/arch/mips/include/asm/mach-loongson64/irq.h > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > @@ -7,7 +7,7 @@ > /* cpu core interrupt numbers */ > #define NR_IRQS_LEGACY 16 > #define NR_MIPS_CPU_IRQS 8 > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > +#define NR_IRQS 320 > > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256)
What does MIDDLE_IRQS mean? Please name it to something that actually relates to its usage...
INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by
Tell me something I don't know...
middle nodes (not leaf nodes and not root node), midde nodes is not directed by devices, but they consumes irq numbers.
Then name the #define something that represents its use. "middle" doesn't describe anything. Call it "chained", or "cascade", or something at actually reflects the topology of these systems.
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ.
It'd be worth considering putting some efforts there...
Yes, but that is another topic.
It really is the same topic. You keep bumping this NR_IRQS up in arbitrary ways, which would be avoided if you brought MIPS into the 21st century.
M.
Hi, Marc,
On Fri, Sep 11, 2020 at 5:23 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 10:14, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 09:43, Huacai Chen wrote:
Hi, Marc,
On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-11 04:24, Huacai Chen wrote:
Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote: > > On 2020-09-09 05:09, Huacai Chen wrote: > > Modernized Loongson64 uses a hierarchical organization for interrupt > > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > > is not enough to represent all interrupts, so let's increase NR_IRQS to > > 320. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Huacai Chen chenhc@lemote.com > > --- > > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > > b/arch/mips/include/asm/mach-loongson64/irq.h > > index f5e362f7..0da3017 100644 > > --- a/arch/mips/include/asm/mach-loongson64/irq.h > > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > > @@ -7,7 +7,7 @@ > > /* cpu core interrupt numbers */ > > #define NR_IRQS_LEGACY 16 > > #define NR_MIPS_CPU_IRQS 8 > > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > > +#define NR_IRQS 320 > > > > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY > > Why are you hardcoding a random value instead of bumping the constant > in NR_IRQS? Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256)
What does MIDDLE_IRQS mean? Please name it to something that actually relates to its usage...
INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by
Tell me something I don't know...
middle nodes (not leaf nodes and not root node), midde nodes is not directed by devices, but they consumes irq numbers.
Then name the #define something that represents its use. "middle" doesn't describe anything. Call it "chained", or "cascade", or something at actually reflects the topology of these systems.
I choose "chained".
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward.
I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ.
It'd be worth considering putting some efforts there...
Yes, but that is another topic.
It really is the same topic. You keep bumping this NR_IRQS up in arbitrary ways, which would be avoided if you brought MIPS into the 21st century.
Jiaxun, please explain why you don't use SPARSE_IRQ?
Huacai
M.-- Jazz is not dead. It just smells funny...
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Failed to apply! Possible dependencies: 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v5.4.63: Failed to apply! Possible dependencies: 268a2d600130 ("MIPS: Loongson64: Rename CPU TYPES") 39b2d7565a47 ("MIPS: Kconfig: always select ARC_MEMORY and ARC_PROMLIB for platform") 6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory") 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64") 7505576d1c1a ("MIPS: add support for SGI Octane (IP30)") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 8bec3875c547 ("MIPS: Loongson64: Drop legacy IRQ code") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v4.19.143: Failed to apply! Possible dependencies: 05a0a3441869 ("rtc: mips: default to rtc-cmos on mips") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.14.196: Failed to apply! Possible dependencies: 3d8757b87d7f ("s390/sthyi: add s390_sthyi system call") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 71406883fd35 ("s390/kexec_file: Add kexec_file_load system call") 840798a1f529 ("s390/kexec_file: Add purgatory") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 8e6d08e0a15e ("openrisc: initial SMP support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") 9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info") b7c92f1a4e13 ("s390/sthyi: reorganize sthyi implementation") c33eff600584 ("s390/perf: add perf_regs support and user stack dump") e71ea3badae5 ("nds32: Build infrastructure") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") fbe934d69eb7 ("RISC-V: Build Infrastructure")
v4.9.235: Failed to apply! Possible dependencies: 043b42bcbbc6 ("arch/openrisc: add option to skip DMA sync as a part of mapping") 07c75d7a6b9e ("drivers: dma-mapping: allow dma_common_mmap() for NOMMU") 266c7fad1572 ("openrisc: Consolidate setup to use memblock instead of bootmem") 34bbdcdcda88 ("openrisc: add NR_CPUS Kconfig default value") 3e06a1633930 ("openrisc: add cache way information to cpuinfo") 550116d21a65 ("scripts/spelling.txt: add "aligment" pattern and fix typo instances") 63104c06a9ed ("openrisc: add l.lwa/l.swa emulation") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") 7844572c6339 ("lib/dma-noop: Only build dma_noop_ops for s390 and m32r") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 8c9b7db0de3d ("openrisc: head: refactor out tlb flush into it's own function") 8e6d08e0a15e ("openrisc: initial SMP support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") e1231b0e487c ("s390: add cma support") e71ea3badae5 ("nds32: Build infrastructure") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.4.235: Failed to apply! Possible dependencies: 0d4a619b64ba ("dma-mapping: make the generic coherent dma mmap implementation optional") 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.") 37eda9df5bd8 ("ARC: mm: Introduce explicit super page size support") 42b510eb56de ("h8300: Add LZO compression") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") 79387179e2e4 ("parisc: convert to dma_map_ops") 7af3a0a99252 ("arm64/numa: support HAVE_SETUP_PER_CPU_AREA") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 910cd32e552e ("parisc: Fix and enable seccomp filter support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") 96ff2d7081cf ("h8300: Add KGDB support.") 97a23beb8db9 ("clocksource/drivers/h8300_timer8: Separate the Kconfig option from the arch") da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") fff7fb0b2d90 ("lib/GCD.c: use binary GCD algorithm instead of Euclidean")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
Hi, Sasha,
On Fri, Sep 11, 2020 at 1:21 AM Sasha Levin sashal@kernel.org wrote:
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag. The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Failed to apply! Possible dependencies: 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v5.4.63: Failed to apply! Possible dependencies: 268a2d600130 ("MIPS: Loongson64: Rename CPU TYPES") 39b2d7565a47 ("MIPS: Kconfig: always select ARC_MEMORY and ARC_PROMLIB for platform") 6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory") 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64") 7505576d1c1a ("MIPS: add support for SGI Octane (IP30)") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 8bec3875c547 ("MIPS: Loongson64: Drop legacy IRQ code") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v4.19.143: Failed to apply! Possible dependencies: 05a0a3441869 ("rtc: mips: default to rtc-cmos on mips") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.14.196: Failed to apply! Possible dependencies: 3d8757b87d7f ("s390/sthyi: add s390_sthyi system call") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 71406883fd35 ("s390/kexec_file: Add kexec_file_load system call") 840798a1f529 ("s390/kexec_file: Add purgatory") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 8e6d08e0a15e ("openrisc: initial SMP support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") 9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info") b7c92f1a4e13 ("s390/sthyi: reorganize sthyi implementation") c33eff600584 ("s390/perf: add perf_regs support and user stack dump") e71ea3badae5 ("nds32: Build infrastructure") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") fbe934d69eb7 ("RISC-V: Build Infrastructure")
v4.9.235: Failed to apply! Possible dependencies: 043b42bcbbc6 ("arch/openrisc: add option to skip DMA sync as a part of mapping") 07c75d7a6b9e ("drivers: dma-mapping: allow dma_common_mmap() for NOMMU") 266c7fad1572 ("openrisc: Consolidate setup to use memblock instead of bootmem") 34bbdcdcda88 ("openrisc: add NR_CPUS Kconfig default value") 3e06a1633930 ("openrisc: add cache way information to cpuinfo") 550116d21a65 ("scripts/spelling.txt: add "aligment" pattern and fix typo instances") 63104c06a9ed ("openrisc: add l.lwa/l.swa emulation") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") 7844572c6339 ("lib/dma-noop: Only build dma_noop_ops for s390 and m32r") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 8c9b7db0de3d ("openrisc: head: refactor out tlb flush into it's own function") 8e6d08e0a15e ("openrisc: initial SMP support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") e1231b0e487c ("s390: add cma support") e71ea3badae5 ("nds32: Build infrastructure") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.4.235: Failed to apply! Possible dependencies: 0d4a619b64ba ("dma-mapping: make the generic coherent dma mmap implementation optional") 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.") 37eda9df5bd8 ("ARC: mm: Introduce explicit super page size support") 42b510eb56de ("h8300: Add LZO compression") 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") 79387179e2e4 ("parisc: convert to dma_map_ops") 7af3a0a99252 ("arm64/numa: support HAVE_SETUP_PER_CPU_AREA") 863be3c3ab73 ("MIPS: Add header files reference with path prefix") 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") 910cd32e552e ("parisc: Fix and enable seccomp filter support") 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") 96ff2d7081cf ("h8300: Add KGDB support.") 97a23beb8db9 ("clocksource/drivers/h8300_timer8: Separate the Kconfig option from the arch") da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") fff7fb0b2d90 ("lib/GCD.c: use binary GCD algorithm instead of Euclidean")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
I'm sorry that this patch is only needed in 5.9+, please ignore my noise.
Huacai
-- Thanks Sasha
linux-stable-mirror@lists.linaro.org
-
Huacai Chen -
Jiaxun Yang -
Marc Zyngier -
Sasha Levin