When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup() before configuring ECAM iATU entries. This left IO and MEM outbound windows unprogrammed, resulting in broken IO transactions. Additionally, dw_pcie_config_ecam_iatu() was only called during host initialization, so ECAM-related iATU entries were not restored after suspend/resume, leading to failures in configuration space access.
To resolve these issues, the ECAM iATU configuration is moved into dw_pcie_setup_rc(). At the same time, dw_pcie_iatu_setup() is invoked when ECAM is enabled.
Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com --- Changes in v2: - Fixed the index 0 of the ATU window skipping. - Keep the ob_atu_index in dw_pcie instead of dw_pcie_rp & couple of nitpicks (Bjorn). - Link to v1: https://lore.kernel.org/r/20251203-ecam_io_fix-v1-0-5cc3d3769c18@oss.qualcom...
--- Krishna Chaitanya Chundru (3): PCI: dwc: Fix skipped index 0 in outbound ATU setup PCI: dwc: Correct iATU index increment for MSG TLP region PCI: dwc: Fix missing iATU setup when ECAM is enabled
drivers/pci/controller/dwc/pcie-designware-host.c | 53 ++++++++++++++--------- drivers/pci/controller/dwc/pcie-designware.c | 3 ++ drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 37 insertions(+), 21 deletions(-) --- base-commit: 3f9f0252130e7dd60d41be0802bf58f6471c691d change-id: 20251203-ecam_io_fix-6e060fecd3b8
Best regards,
Commit e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend") introduced a mechanism to reserve an iATU window for MSG TLP transactions. However, the code incorrectly assigned pp->msg_atu_index = i without incrementing i first, causing the MSG TLP region to reuse the last configured outbound window instead of the next available one. This can cause issue with IO transfers as this can over write iATU configured for IO memory.
Fix this by incrementing i before assigning it to msg_atu_index so that the MSG TLP region uses a dedicated iATU entry.
Added error logs in dw_pcie_pme_turn_off().
Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend") Tested-by: Maciej W. Rozycki macro@orcam.me.uk Reviewed-by: Frank Li Frank.Li@nxp.com Cc: stable@vger.kernel.org Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 32a26458ed8f1696fe2fdcf9df6b795c4c761f1f..88b6ace0607e97bf6dd6bf7886baaa13bf267e6e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -942,7 +942,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows);
- pp->msg_atu_index = i; + pp->msg_atu_index = ++i;
i = 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { @@ -1113,11 +1113,15 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) void __iomem *mem; int ret;
- if (pci->num_ob_windows <= pci->pp.msg_atu_index) + if (pci->num_ob_windows <= pci->pp.msg_atu_index) { + dev_err(pci->dev, "No available iATU enteries\n"); return -ENOSPC; + }
- if (!pci->pp.msg_res) + if (!pci->pp.msg_res) { + dev_err(pci->dev, "Msg resource is not allocated\n"); return -ENOSPC; + }
atu.code = PCIE_MSG_CODE_PME_TURN_OFF; atu.routing = PCIE_MSG_TYPE_R_BC;
In dw_pcie_iatu_setup(), the outbound ATU loop uses a pre-increment on the index and starts programming from 1, effectively skipping index 0. This results in the first outbound window never being configured.
Update the logic to start from index 0 and use post-increment (i++) when assigning atu.index.
Fixes: ce06bf570390f ("PCI: dwc: Check iATU in/outbound range setup status") Cc: stable@vger.kernel.org Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com --- Note:- The fix tag shown above is for applying this patch cleanly, further below versions we need to manually apply them, If any one intrested to apply this fix then we can submit another patch based on that kernel version. --- drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index e92513c5bda51bde3a7157033ddbd73afa370d78..32a26458ed8f1696fe2fdcf9df6b795c4c761f1f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -896,10 +896,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (resource_type(entry->res) != IORESOURCE_MEM) continue;
- if (pci->num_ob_windows <= ++i) + if (pci->num_ob_windows < i) break;
- atu.index = i; + atu.index = i++; atu.type = PCIE_ATU_TYPE_MEM; atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; atu.pci_addr = entry->res->start - entry->offset; @@ -920,7 +920,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) }
if (pp->io_size) { - if (pci->num_ob_windows > ++i) { + if (pci->num_ob_windows > i) { atu.index = i; atu.type = PCIE_ATU_TYPE_IO; atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
linux-stable-mirror@lists.linaro.org
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Krishna Chaitanya Chundru