With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Applying this configuration permits correct functionality of any externally attached PHY.
Cc: stable@vger.kernel.org Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index f7f8fd2f35fc..d89da9581c55 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -108,6 +108,9 @@ #define JTAG_UDI_EN_MASK BIT(4) #define JTAG_DFD_EN_MASK BIT(3)
+#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + /* LED MAP */ #define REG_LAN_LED0_MAPPING 0x027c #define REG_LAN_LED1_MAPPING 0x0280 @@ -718,17 +721,17 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = { { .name = "mdio", .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SGMII_MDIO_MODE_MASK, - GPIO_SGMII_MDIO_MODE_MASK - }, - .regmap[1] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, GPIO_MDC_IO_MASTER_MODE_MODE, GPIO_MDC_IO_MASTER_MODE_MODE }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO_EN, + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) + }, .regmap_size = 2, }, };
On 2025-09-08 13:37, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Applying this configuration permits correct functionality of any externally attached PHY.
Hi, the hardware design guide mentions that gpio1 and gpio2 has some limitations when the mdio function is used and there is a chip errata for the 7581 that also mentions mdio. This indicates that the SoC has issues with mdio function to pin routing.
During my testing it seemed like the gpio1 and gpio2 pins where bridged to the mdc/mdio pins (they are not the same). When setting force enable on gpio1/gpio2 the bridging stopped and the pins seemed to return to the gpio1/2 function. Without the force enable set my guess is that the bridged gpio pins pull-up or pull-down is enough to interfere with mdio bus signal integrity causing the external phy issues.
Thus ACK from me to this change.
MvH
Benjamin Larsson
On Mon, Sep 8, 2025 at 1:37 PM Christian Marangi ansuelsmth@gmail.com wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Applying this configuration permits correct functionality of any externally attached PHY.
Cc: stable@vger.kernel.org Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Christian Marangi ansuelsmth@gmail.com
Patch applied, recorded Benjamins response as Acked-by.
Yours, Linus Walleij
On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Is the MDIO bus implemented using the GPIO bitbanging driver?
Andrew
On Mon, Sep 08, 2025 at 06:54:15PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Is the MDIO bus implemented using the GPIO bitbanging driver?
No it does use the MDIO bus integrated in the MT7530 Switch. It's just that the MDIO pin can be muxed as GPIO usage.
On Mon, Sep 08, 2025 at 07:48:17PM +0200, Christian Marangi wrote:
On Mon, Sep 08, 2025 at 06:54:15PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Is the MDIO bus implemented using the GPIO bitbanging driver?
No it does use the MDIO bus integrated in the MT7530 Switch. It's just that the MDIO pin can be muxed as GPIO usage.
Then i do not understand this patch. Why configure the pinmux for GPIO when you want it connected to the MDIO bus device?
Andrew
On Mon, Sep 08, 2025 at 09:06:03PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 07:48:17PM +0200, Christian Marangi wrote:
On Mon, Sep 08, 2025 at 06:54:15PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Is the MDIO bus implemented using the GPIO bitbanging driver?
No it does use the MDIO bus integrated in the MT7530 Switch. It's just that the MDIO pin can be muxed as GPIO usage.
Then i do not understand this patch. Why configure the pinmux for GPIO when you want it connected to the MDIO bus device?
The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines.
Normally the SoC should autodetect this by HW but it seems AN7581 have problem with this and require this workaround to force enable the 2 pin.
On Mon, Sep 08, 2025 at 09:14:49PM +0200, Christian Marangi wrote:
On Mon, Sep 08, 2025 at 09:06:03PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 07:48:17PM +0200, Christian Marangi wrote:
On Mon, Sep 08, 2025 at 06:54:15PM +0200, Andrew Lunn wrote:
On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits.
Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin.
Is the MDIO bus implemented using the GPIO bitbanging driver?
No it does use the MDIO bus integrated in the MT7530 Switch. It's just that the MDIO pin can be muxed as GPIO usage.
Then i do not understand this patch. Why configure the pinmux for GPIO when you want it connected to the MDIO bus device?
The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines.
So please extent the commit message: FORCE_GPIO_EN does not actually force the pin to GPIO, but really means....
The commit message is the correct place to try to explain why the patch makes no sense, because FORCE_GPIO_EN is wrongly named.
Andrew
On Mon, Sep 8, 2025 at 9:14 PM Christian Marangi ansuelsmth@gmail.com wrote:
The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines.
Normally the SoC should autodetect this by HW but it seems AN7581 have problem with this and require this workaround to force enable the 2 pin.
In reply to Andrews comment I copied the two above paragraphs into the commit message in the applied patch.
Yours, Linus Walleij
On Mon, Sep 08, 2025 at 11:03:31PM +0200, Linus Walleij wrote:
On Mon, Sep 8, 2025 at 9:14 PM Christian Marangi ansuelsmth@gmail.com wrote:
The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines.
Normally the SoC should autodetect this by HW but it seems AN7581 have problem with this and require this workaround to force enable the 2 pin.
In reply to Andrews comment I copied the two above paragraphs into the commit message in the applied patch.
Thanks for handling this and adding the extra info, I was about to send v2.
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Linus Walleij