As mentioned in Erratum 1583 from the Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors available at the link below, PMCx18E reports incorrect information about instruction cache accesses on Zen 5 processors. Remove affected events and metrics.

Link: https://bugzilla.kernel.org/attachment.cgi?id=308095 Fixes: 45c072f2537a ("perf vendor events amd: Add Zen 5 core events") Signed-off-by: Sandipan Das sandipan.das@amd.com Cc: stable@vger.kernel.org --- .../arch/x86/amdzen5/inst-cache.json | 18 ------------------ .../arch/x86/amdzen5/recommended.json | 6 ------ 2 files changed, 24 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/amdzen5/inst-cache.json b/tools/perf/pmu-events/arch/x86/amdzen5/inst-cache.json index ad75e5bf9513..4fd5e2c5432f 100644 --- a/tools/perf/pmu-events/arch/x86/amdzen5/inst-cache.json +++ b/tools/perf/pmu-events/arch/x86/amdzen5/inst-cache.json @@ -33,24 +33,6 @@ "BriefDescription": "Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt.", "UMask": "0x10" }, - { - "EventName": "ic_tag_hit_miss.instruction_cache_hit", - "EventCode": "0x18e", - "BriefDescription": "Instruction cache hits.", - "UMask": "0x07" - }, - { - "EventName": "ic_tag_hit_miss.instruction_cache_miss", - "EventCode": "0x18e", - "BriefDescription": "Instruction cache misses.", - "UMask": "0x18" - }, - { - "EventName": "ic_tag_hit_miss.all_instruction_cache_accesses", - "EventCode": "0x18e", - "BriefDescription": "Instruction cache accesses of all types.", - "UMask": "0x1f" - }, { "EventName": "op_cache_hit_miss.op_cache_hit", "EventCode": "0x28f", diff --git a/tools/perf/pmu-events/arch/x86/amdzen5/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen5/recommended.json index 635d57e3bc15..863f4b5dfc14 100644 --- a/tools/perf/pmu-events/arch/x86/amdzen5/recommended.json +++ b/tools/perf/pmu-events/arch/x86/amdzen5/recommended.json @@ -136,12 +136,6 @@ "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)", "ScaleUnit": "100%" }, - { - "MetricName": "ic_fetch_miss_ratio", - "BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.", - "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)", - "ScaleUnit": "100%" - }, { "MetricName": "l1_data_cache_fills_from_memory_pti", "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions.",