[PATCH 6.1.y] spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
From: Steve Wilkins steve.wilkins@raymarine.com
[ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ]
While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Steve Wilkins steve.wilkins@raymarine.com Signed-off-by: Conor Dooley conor.dooley@microchip.com Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy Signed-off-by: Mark Brown broonie@kernel.org [Minor conflict resolved due to code context change.] Signed-off-by: Jianqi Ren jianqi.ren.cn@windriver.com Signed-off-by: He Zhe zhe.he@windriver.com --- Verified the build test --- drivers/spi/spi-microchip-core.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index bfad0fe743ad..acc05f5a929e 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -91,6 +91,8 @@ #define REG_CONTROL2 (0x28) #define REG_COMMAND (0x2c) #define COMMAND_CLRFRAMECNT BIT(4) +#define COMMAND_TXFIFORST BIT(3) +#define COMMAND_RXFIFORST BIT(2) #define REG_PKTSIZE (0x30) #define REG_CMD_SIZE (0x34) #define REG_HWSTATUS (0x38) @@ -489,6 +491,8 @@ static int mchp_corespi_transfer_one(struct spi_controller *host, mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH) ? FIFO_DEPTH : spi->tx_len);
+ mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST); + while (spi->tx_len) mchp_corespi_write_fifo(spi);
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected. No action required from the submitter.
The upstream commit SHA1 provided is correct: 9cf71eb0faef4bff01df4264841b8465382d7927
WARNING: Author mismatch between patch and upstream commit: Backport author: jianqi.ren.cn@windriver.com Commit author: Steve Wilkinssteve.wilkins@raymarine.com
Status in newer kernel trees: 6.14.y | Present (exact SHA1) 6.12.y | Present (exact SHA1) 6.6.y | Present (different SHA1: 3feda3677e8b)
Note: The patch differs from the upstream commit: --- 1: 9cf71eb0faef4 ! 1: e2b7a4dc57e1d spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer @@ Metadata ## Commit message ## spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
+ [ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ] + While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the @@ Commit message Signed-off-by: Conor Dooley conor.dooley@microchip.com Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy Signed-off-by: Mark Brown broonie@kernel.org + [Minor conflict resolved due to code context change.] + Signed-off-by: Jianqi Ren jianqi.ren.cn@windriver.com + Signed-off-by: He Zhe zhe.he@windriver.com
## drivers/spi/spi-microchip-core.c ## @@ @@ drivers/spi/spi-microchip-core.c: static int mchp_corespi_transfer_one(struct sp
+ mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST); + - mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); - while (spi->tx_len) + mchp_corespi_write_fifo(spi); + ---
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.1.y | Success | Success |
HIiall,
Why isn't this patch being applied? If you have forgotten, could you please apply this?
Best regards, Nobuhiro
2025年5月13日(火) 6:52 Sasha Levin sashal@kernel.org:
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected. No action required from the submitter.
The upstream commit SHA1 provided is correct: 9cf71eb0faef4bff01df4264841b8465382d7927
WARNING: Author mismatch between patch and upstream commit: Backport author: jianqi.ren.cn@windriver.com Commit author: Steve Wilkinssteve.wilkins@raymarine.com
Status in newer kernel trees: 6.14.y | Present (exact SHA1) 6.12.y | Present (exact SHA1) 6.6.y | Present (different SHA1: 3feda3677e8b)
Note: The patch differs from the upstream commit:
1: 9cf71eb0faef4 ! 1: e2b7a4dc57e1d spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer @@ Metadata ## Commit message ## spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
+ [ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ] + While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the @@ Commit message Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy Signed-off-by: Mark Brown <broonie@kernel.org> + [Minor conflict resolved due to code context change.] + Signed-off-by: Jianqi Ren <jianqi.ren.cn@windriver.com> + Signed-off-by: He Zhe <zhe.he@windriver.com> ## drivers/spi/spi-microchip-core.c ## @@ @@ drivers/spi/spi-microchip-core.c: static int mchp_corespi_transfer_one(struct sp + mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST); + - mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); - while (spi->tx_len) + mchp_corespi_write_fifo(spi); +
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.1.y | Success | Success |
On Thu, Oct 09, 2025 at 09:35:21PM +0900, Nobuhiro Iwamatsu wrote:
HIiall,
Why isn't this patch being applied?
Perhaps because I had to drop ALL windriver submissions due to them not working at all. This was in that batch. See the mailing list archives for details.
If you think this needs to be applied, please test it yourself and submit it with your signed-off-by please.
thanks,
greg k-h
linux-stable-mirror@lists.linaro.org
-
Greg Kroah-Hartman -
jianqi.ren.cn＠windriver.com -
Nobuhiro Iwamatsu -
Sasha Levin