From: Mark Zhang markz@nvidia.com
commit 7151449fe7fa5962c6153355f9779d6be99e8e97 upstream.
If client have not provided the mask base register then do not write into the mask register.
Signed-off-by: Laxman Dewangan ldewangan@nvidia.com Signed-off-by: Jinyoung Park jinyoungp@nvidia.com Signed-off-by: Venkat Reddy Talla vreddytalla@nvidia.com Signed-off-by: Mark Zhang markz@nvidia.com Signed-off-by: Mark Brown broonie@kernel.org --- This commit was found in an nVidia product tree based on v4.19, and looks like definitive stable material to me. It should go into v4.19 only as far as I can tell. --- drivers/base/regmap/regmap-irq.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 429ca8ed7e51..982c7ac311b8 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -91,6 +91,9 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * suppress pointless writes. */ for (i = 0; i < d->chip->num_regs; i++) { + if (!d->chip->mask_base) + continue; + reg = d->chip->mask_base + (i * map->reg_stride * d->irq_reg_stride); if (d->chip->mask_invert) { @@ -526,6 +529,9 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, /* Mask all the interrupts by default */ for (i = 0; i < chip->num_regs; i++) { d->mask_buf[i] = d->mask_buf_def[i]; + if (!chip->mask_base) + continue; + reg = chip->mask_base + (i * map->reg_stride * d->irq_reg_stride); if (chip->mask_invert)
Hi Greg,
On Mon, May 20, 2019 at 7:23 PM Linus Walleij linus.walleij@linaro.org wrote:
From: Mark Zhang markz@nvidia.com
commit 7151449fe7fa5962c6153355f9779d6be99e8e97 upstream.
If client have not provided the mask base register then do not write into the mask register.
Signed-off-by: Laxman Dewangan ldewangan@nvidia.com Signed-off-by: Jinyoung Park jinyoungp@nvidia.com Signed-off-by: Venkat Reddy Talla vreddytalla@nvidia.com Signed-off-by: Mark Zhang markz@nvidia.com Signed-off-by: Mark Brown broonie@kernel.org
This commit was found in an nVidia product tree based on v4.19, and looks like definitive stable material to me. It should go into v4.19 only as far as I can tell.
Was this missed or is there some reason for why this didn't get queued to stable?
Yours, Linus Walleij
On Wed, Jul 17, 2019 at 09:42:00AM +0200, Linus Walleij wrote:
Hi Greg,
On Mon, May 20, 2019 at 7:23 PM Linus Walleij linus.walleij@linaro.org wrote:
From: Mark Zhang markz@nvidia.com
commit 7151449fe7fa5962c6153355f9779d6be99e8e97 upstream.
If client have not provided the mask base register then do not write into the mask register.
Signed-off-by: Laxman Dewangan ldewangan@nvidia.com Signed-off-by: Jinyoung Park jinyoungp@nvidia.com Signed-off-by: Venkat Reddy Talla vreddytalla@nvidia.com Signed-off-by: Mark Zhang markz@nvidia.com Signed-off-by: Mark Brown broonie@kernel.org
This commit was found in an nVidia product tree based on v4.19, and looks like definitive stable material to me. It should go into v4.19 only as far as I can tell.
Was this missed or is there some reason for why this didn't get queued to stable?
I think it was missed, sorry :(
Now queued up.
greg k-h
On Wed, Jul 17, 2019 at 04:54:17PM +0900, Greg Kroah-Hartman wrote:
On Wed, Jul 17, 2019 at 09:42:00AM +0200, Linus Walleij wrote:
Hi Greg,
On Mon, May 20, 2019 at 7:23 PM Linus Walleij linus.walleij@linaro.org wrote:
From: Mark Zhang markz@nvidia.com
commit 7151449fe7fa5962c6153355f9779d6be99e8e97 upstream.
If client have not provided the mask base register then do not write into the mask register.
Signed-off-by: Laxman Dewangan ldewangan@nvidia.com Signed-off-by: Jinyoung Park jinyoungp@nvidia.com Signed-off-by: Venkat Reddy Talla vreddytalla@nvidia.com Signed-off-by: Mark Zhang markz@nvidia.com Signed-off-by: Mark Brown broonie@kernel.org
This commit was found in an nVidia product tree based on v4.19, and looks like definitive stable material to me. It should go into v4.19 only as far as I can tell.
Was this missed or is there some reason for why this didn't get queued to stable?
I think it was missed, sorry :(
Found it, it was burried in my "to-queue" stable mbox, thanks for resending.
greg k-h
linux-stable-mirror@lists.linaro.org