Purpose is to add ad3552r AXI DAC (fpga-based) support.
The "ad3552r" AXI IP, a variant of the generic "DAC" AXI IP, has been created to reach the maximum speed (33MUPS) supported from the ad3552r. To obtain the maximum transfer rate, a custom IP core module has been implemented with a QSPI interface with DDR (Double Data Rate) mode.
The design is actually using the DAC backend since the register map is the same of the generic DAC IP, except for some customized bitfields. For this reason, a new "compatible" has been added in adi-axi-dac.c.
Also, backend has been extended with all the needed functions for this use case, keeping the names gneric.
The following patch is actually applying to linux-iio/testing.
--- Changes in v2: - use unsigned int on bus_reg_read/write - add a compatible in axi-dac backend for the ad3552r DAC IP - minor code alignment fixes - fix a return value not checked - change devicetree structure setting ad3552r-axi as a backend subnode - add synchronous_mode_available in the ABI doc
Changes in v3: - changing AXI backend approach using a dac ip compatible - fdt bindings updates accordingly - fdt, ad3552r device must be a subnode of the backend - allow probe of child devices - passing QSPI bus access function by platform data - move synchronous mode as a fdt parameter - reorganizing defines in proper patches - fix make dt_binding_check errors - fix ad3552r maximum SPI speed - fix samplerate calulcation - minor code style fixes
Changes in v4: - fix Kconfig - fix backend documentation - driver renamed to a more gneric "high speed" (ad3552r-hs) - restyled axi-dac register names - removed synchronous support, dead code (could be added in the future with David sugestions if needed) - renaming backend buffer enable/disable calls - using model_data in common code - using devm_add_action_or_reset - minor code style fixes
Signed-off-by: Angelo Dureghello adureghello@baylibre.com
--- Angelo Dureghello (11): iio: dac: adi-axi-dac: update register names iio: dac: adi-axi-dac: fix wrong register bitfield dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant dt-bindings: iio: dac: ad3552r: fix maximum spi speed dt-bindings: iio: dac: ad3552r: add iio backend support iio: backend: extend features iio: dac: adi-axi-dac: extend features iio: dac: ad3552r: changes to use FIELD_PREP iio: dac: ad3552r: extract common code (no changes in behavior intended) iio: dac: ad3552r: add high-speed platform driver iio: dac: adi-axi-dac: add registering of child fdt node
.../devicetree/bindings/iio/dac/adi,ad3552r.yaml | 9 +- .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 49 +- drivers/iio/dac/Kconfig | 14 + drivers/iio/dac/Makefile | 3 +- drivers/iio/dac/ad3552r-common.c | 170 +++++++ drivers/iio/dac/ad3552r-hs.c | 528 +++++++++++++++++++++ drivers/iio/dac/ad3552r.c | 461 +++--------------- drivers/iio/dac/ad3552r.h | 207 ++++++++ drivers/iio/dac/adi-axi-dac.c | 477 ++++++++++++++++--- drivers/iio/industrialio-backend.c | 79 +++ include/linux/iio/backend.h | 17 + include/linux/platform_data/ad3552r-hs.h | 18 + 12 files changed, 1563 insertions(+), 469 deletions(-) --- base-commit: c81ca31b5191ef48b5e5fb2545fde7dd436c2bd5 change-id: 20241003-wip-bl-ad3552r-axi-v0-iio-testing-aedec3e91ff7
Best regards,
From: Angelo Dureghello adureghello@baylibre.com
Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.
Both generic DAC and ad3552r DAC IPs docs are reporting bit 5 for it.
Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip Fixes: 4e3949a192e4 ("iio: dac: add support for AXI DAC IP core") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com Reviewed-by: Nuno Sa nuno.sa@analog.com --- drivers/iio/dac/adi-axi-dac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index e83f70465b46..04193a98616e 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -46,7 +46,7 @@ #define AXI_DAC_CNTRL_1_REG 0x0044 #define AXI_DAC_CNTRL_1_SYNC BIT(0) #define AXI_DAC_CNTRL_2_REG 0x0048 -#define ADI_DAC_CNTRL_2_R1_MODE BIT(4) +#define ADI_DAC_CNTRL_2_R1_MODE BIT(5) #define AXI_DAC_DRP_STATUS_REG 0x0074 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)
On Thu, 03 Oct 2024 19:28:59 +0200 Angelo Dureghello adureghello@baylibre.com wrote:
From: Angelo Dureghello adureghello@baylibre.com
Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.
Both generic DAC and ad3552r DAC IPs docs are reporting bit 5 for it.
Reorder to come before the previous patch. This want's backporting. The renames are good but too noisy to backport if we can avoid it.
Jonathan
Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip Fixes: 4e3949a192e4 ("iio: dac: add support for AXI DAC IP core") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com Reviewed-by: Nuno Sa nuno.sa@analog.com
drivers/iio/dac/adi-axi-dac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index e83f70465b46..04193a98616e 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -46,7 +46,7 @@ #define AXI_DAC_CNTRL_1_REG 0x0044 #define AXI_DAC_CNTRL_1_SYNC BIT(0) #define AXI_DAC_CNTRL_2_REG 0x0048 -#define ADI_DAC_CNTRL_2_R1_MODE BIT(4) +#define ADI_DAC_CNTRL_2_R1_MODE BIT(5) #define AXI_DAC_DRP_STATUS_REG 0x0074 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)
From: Angelo Dureghello adureghello@baylibre.com
Fix maximum SPI clock speed, as per datasheet (Rev. B, page 6).
Fixes: b0a96c5f599e ("dt-bindings: iio: dac: Add adi,ad3552r.yaml") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com --- Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index fc8b97f82077..41fe00034742 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -30,7 +30,7 @@ properties: maxItems: 1
spi-max-frequency: - maximum: 30000000 + maximum: 66000000
reset-gpios: maxItems: 1
On Thu, Oct 03, 2024 at 07:29:01PM +0200, Angelo Dureghello wrote:
From: Angelo Dureghello adureghello@baylibre.com
Fix maximum SPI clock speed, as per datasheet (Rev. B, page 6).
Fixes: b0a96c5f599e ("dt-bindings: iio: dac: Add adi,ad3552r.yaml") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com
Acked-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Best regards, Krzysztof
On Thu, 03 Oct 2024 19:29:01 +0200 Angelo Dureghello adureghello@baylibre.com wrote:
From: Angelo Dureghello adureghello@baylibre.com
Fix maximum SPI clock speed, as per datasheet (Rev. B, page 6).
Fixes: b0a96c5f599e ("dt-bindings: iio: dac: Add adi,ad3552r.yaml") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com
I'm going to take this the slow way as it probably doesn't affect any existing DTS so can wait a while and taking it via the fixes branch would slow down the rest of the series.
I am keen though to cut down how many patches are in revisions though so I've picked this one up today. Please rebase on my tree before sending v5 to pick this up.
Applied to the togreg branch of iio.git
Thanks, Jonathan
Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index fc8b97f82077..41fe00034742 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -30,7 +30,7 @@ properties: maxItems: 1 spi-max-frequency:
- maximum: 30000000
- maximum: 66000000
reset-gpios: maxItems: 1
linux-stable-mirror@lists.linaro.org
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Angelo Dureghello -
Jonathan Cameron -
Krzysztof Kozlowski