On 29.08.2018 10:56, kostap@marvell.com wrote:

From: Boris Brezillon boris.brezillon@free-electrons.com

In the current driver, OOB bytes are accessed in raw mode, and when a page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the driver must read the whole spare area (64 bytes in case of a 2k page, 16 bytes for a 512 page). The driver was only reading the free OOB bytes, which was leaving some unread data in the FIFO and was somehow leading to a timeout.

We could patch the driver to read ->spare_size + ->ecc_size instead of just ->spare_size when READOOB is requested, but we'd better make in-band and OOB accesses consistent. Since the driver is always accessing in-band data in non-raw mode (with the ECC engine enabled), we should also access OOB data in this mode. That's particularly useful when using the BCH engine because in this mode the free OOB bytes are also ECC protected.

Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support") Cc: stable@vger.kernel.org Reported-by: Sean Nyekjær sean.nyekjaer@prevas.dk Tested-by: Willy Tarreau w@1wt.eu Signed-off-by: Boris Brezillon boris.brezillon@free-electrons.com Acked-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar Tested-by: Sean Nyekjaer sean.nyekjaer@prevas.dk Acked-by: Robert Jarzmik robert.jarzmik@free.fr Signed-off-by: Richard Weinberger richard@nod.at Signed-off-by: Ofer Heifetz oferh@marvell.com Reviewed-by: Igal Liberman igall@marvell.com Cc: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org

---

drivers/mtd/nand/pxa3xx_nand.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index b64dd0d..c1f7d61 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -750,6 +750,7 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) switch (command) { case NAND_CMD_READ0:

• case NAND_CMD_READOOB: case NAND_CMD_PAGEPROG: info->use_ecc = 1; break;

Applied to u-boot-marvell/master

Thanks, Stefan