On Mon, Sep 16, 2024 at 11:46:02AM +0800, WangYuli wrote:

From: William Qiu william.qiu@starfivetech.com

[ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]

In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency.

Signed-off-by: William Qiu william.qiu@starfivetech.com Reviewed-by: Emil Renner Berthing emil.renner.berthing@canonical.com Signed-off-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: WangYuli wangyuli@uniontech.com

---

.../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 062b97c6e7df..4874e3bb42ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -204,6 +204,8 @@ &i2c6 { &mmc0 { max-frequency = <100000000>;

• assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
• assigned-clock-rates = <50000000>; bus-width = <8>; cap-mmc-highspeed; mmc-ddr-1_8v;

@@ -220,6 +222,8 @@ &mmc0 { &mmc1 { max-frequency = <100000000>;

• assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
• assigned-clock-rates = <50000000>; bus-width = <4>; no-sdio; no-mmc;

-- 2.43.0

Now queued up, thanks.

greg k-h