On Mon, Feb 28, 2022 at 2:18 AM Johan Hovold johan@kernel.org wrote:

Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not muxed for SPI mode and causes reads from a slave-device connected to the SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and gw73xx families of boards that got this wrong.

Fixes: 6f30b27c5ef5 ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits") Cc: stable@vger.kernel.org # 5.12 Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Johan Hovold johan@kernel.org

---

arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 28012279f6f6..ecf6c9a6db90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -166,7 +166,7 @@ pinctrl_spi2: spi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6

•                   MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
  

•                   MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                    MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
            >;
    };
  

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 27afa46a253a..6e0f0a2f6970 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -231,7 +231,7 @@ pinctrl_spi2: spi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6

•                   MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
  

•                   MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                    MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
            >;
    };
  

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index a59e849c7be2..6c4c9ae9715f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -280,7 +280,7 @@ pinctrl_spi2: spi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6

•                   MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
  

•                   MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                    MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
            >;
    };
  

-- 2.34.1

Johan,

Thanks for catching this!

Acked-by: Tim Harvey tharvey@gateworks.com

Best Regards,

Tim