The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 908d969f88bfcf6d8538a0159e502567c7678775 Gitweb: https://git.kernel.org/tip/908d969f88bfcf6d8538a0159e502567c7678775 Author: Borislav Petkov bp@suse.de AuthorDate: Wed, 06 Oct 2021 18:33:52 +02:00 Committer: Borislav Petkov bp@suse.de CommitterDate: Wed, 06 Oct 2021 18:46:06 +02:00
x86/fpu: Restore the masking out of reserved MXCSR bits
Ser Olmy reported a boot failure:
init[1] bad frame in sigreturn frame:(ptrval) ip:b7c9fbe6 sp:bf933310 orax:ffffffff \ in libc-2.33.so[b7bed000+156000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b CPU: 0 PID: 1 Comm: init Tainted: G W 5.14.9 #1 Hardware name: Hewlett-Packard HP PC/HP Board, BIOS JD.00.06 12/06/2001 Call Trace: dump_stack_lvl dump_stack panic do_exit.cold do_group_exit get_signal arch_do_signal_or_restart ? force_sig_info_to_task ? force_sig exit_to_user_mode_prepare syscall_exit_to_user_mode do_int80_syscall_32 entry_INT80_32
on an old 32-bit Intel CPU:
vendor_id : GenuineIntel cpu family : 6 model : 6 model name : Celeron (Mendocino) stepping : 5 microcode : 0x3
Ser bisected the problem to the commit in Fixes.
tglx suggested reverting the rejection of invalid MXCSR values which this commit introduced and replacing it with what the old code did - simply masking them out to zero.
Further debugging confirmed his suggestion:
fpu->state.fxsave.mxcsr: 0xb7be13b4, mxcsr_feature_mask: 0xffbf WARNING: CPU: 0 PID: 1 at arch/x86/kernel/fpu/signal.c:384 __fpu_restore_sig+0x51f/0x540
so restore the original behavior.
Fixes: 6f9866a166cd ("x86/fpu/signal: Let xrstor handle the features to init") Reported-by: Ser Olmy ser.olmy@protonmail.com Signed-off-by: Borislav Petkov bp@suse.de Tested-by: Ser Olmy ser.olmy@protonmail.com Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/YVtA67jImg3KlBTw@zn.tnic --- arch/x86/kernel/fpu/signal.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index 445c57c..684be34 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -379,9 +379,8 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, sizeof(fpu->state.fxsave))) return -EFAULT;
- /* Reject invalid MXCSR values. */ - if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) - return -EINVAL; + /* Mask out reserved MXCSR bits. */ + fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ if (use_xsave())
On Wed, Oct 06 2021 at 17:38, tip-bot wrote:
Ser bisected the problem to the commit in Fixes.
tglx suggested reverting the rejection of invalid MXCSR values which this commit introduced and replacing it with what the old code did - simply masking them out to zero.
Further debugging confirmed his suggestion:
fpu->state.fxsave.mxcsr: 0xb7be13b4, mxcsr_feature_mask: 0xffbf WARNING: CPU: 0 PID: 1 at arch/x86/kernel/fpu/signal.c:384 __fpu_restore_sig+0x51f/0x540
so restore the original behavior.
Fixes: 6f9866a166cd ("x86/fpu/signal: Let xrstor handle the features to init") Reported-by: Ser Olmy ser.olmy@protonmail.com Signed-off-by: Borislav Petkov bp@suse.de Tested-by: Ser Olmy ser.olmy@protonmail.com Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/YVtA67jImg3KlBTw@zn.tnic
arch/x86/kernel/fpu/signal.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index 445c57c..684be34 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -379,9 +379,8 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, sizeof(fpu->state.fxsave))) return -EFAULT;
/* Reject invalid MXCSR values. */
if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
return -EINVAL;
/* Mask out reserved MXCSR bits. */
fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
can we please make this:
--- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -384,9 +384,14 @@ static bool __fpu_restore_sig(void __use sizeof(fpu->state.fxsave))) return false;
- /* Reject invalid MXCSR values. */ - if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) - return false; + if (IS_ENABLED(CONFIG_X86_64)) { + /* Reject invalid MXCSR values. */ + if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) + return false; + } else { + /* Mask invalid bits out for historical reasons (broken hardware) */ + fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; + }
/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ if (use_xsave())
On a 64 bit kernel even 32bit user space which supplies broken mxcsr values has to be considered malicious.
The 32bit story on those stone age machines is different because the hardware is simply buggy and we can't differentiate between broken hardware and broken or malicious software.
Thanks,
tglx
linux-stable-mirror@lists.linaro.org