On 2020-03-02 10:48, Eric Auger wrote:

commit 3837407c1aa1 upstream.

The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1 if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR.

For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to be set for the corresponding event counter but we also need the PMCR.E bit to be set.

Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register") Signed-off-by: Eric Auger eric.auger@redhat.com Cc: stable@vger.kernel.org # 4.9 and 4.14 only

Reviewed-by: Marc Zyngier maz@kernel.org

---

This is a backport of 3837407c1aa1 ("KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset") which did not apply on 4.9-stable and 4.14-stable trees. Compared to the original patch __vcpu_sys_reg() is replaced by vcpu_sys_reg().

v1 -> v2:

• this patch also is candidate for 4.9-stable

---

virt/kvm/arm/pmu.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 69ccce308458..9a47b0cfb01d 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -299,6 +299,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) if (val == 0) return;

• if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))

• return;
  

• enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) { if (!(val & BIT(i)))