The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250, instead of proper pin gpa1-5.
Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..d7d756614edd 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus { };
uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; + samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
Each pin configuration in pin controller should be a node with "samsung,pins" and other similar properties. However the macro PIN() (used for initial/sleep states) defines entire node, so PCIe WLAN pin configuration node was ignored.
Fixes: 98c03b6eef3f ("arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cbcc01a66aab..c5054c7a9c03 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -1104,8 +1104,11 @@ &pinctrl_ese { pinctrl-names = "default"; pinctrl-0 = <&initial_ese>;
- pcie_wlanen: pcie-wlanen { - PIN(INPUT, gpj2-0, UP, FAST_SR4); + pcie_wlanen: pcie-wlanen-pins { + samsung,pins = "gpj2-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>; };
initial_ese: initial-state {
On 30/12/2021 20:53, Krzysztof Kozlowski wrote:
Each pin configuration in pin controller should be a node with "samsung,pins" and other similar properties. However the macro PIN() (used for initial/sleep states) defines entire node, so PCIe WLAN pin configuration node was ignored.
Fixes: 98c03b6eef3f ("arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
This patch is not correct, because the driver/bindings allow and work with such DTS. Please ignore.
Best regards, Krzysztof
Hi Krzysztof
On Fri, Dec 31, 2021 at 4:02 PM Krzysztof Kozlowski krzysztof.kozlowski@canonical.com wrote:
The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250, instead of proper pin gpa1-5.
Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
Thanks for fixing this. Reviewed-by: Alim Akhtar alim.akhtar@samsung.com
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..d7d756614edd 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus { };
uart3_data: uart3-data {
samsung,pins = "gpa1-4", "gpa1-4";
samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-- 2.32.0
On 30.12.2021 20:53, Krzysztof Kozlowski wrote:
The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250, instead of proper pin gpa1-5.
Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
Well, the uart3_data node is not referenced anywhere, so this change is not really relevant to any board, but for the completeness, feel free to add:
Tested-by: Marek Szyprowski m.szyprowski@samsung.com
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..d7d756614edd 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus { }; uart3_data: uart3-data {
samsung,pins = "gpa1-4", "gpa1-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;samsung,pins = "gpa1-4", "gpa1-5";
Best regards
On Thu, 30 Dec 2021 20:53:23 +0100, Krzysztof Kozlowski wrote:
The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250, instead of proper pin gpa1-5.
Applied, thanks!
[1/3] ARM: dts: exynos: fix UART3 pins configuration in Exynos5250 commit: 372d7027fed43c8570018e124cf78b89523a1f8e
Best regards,
linux-stable-mirror@lists.linaro.org